MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 555

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

be processed. Writing to this register causes the AESU to process the final block of a message, allowing it
to signal DONE. A read of this register will always return a zero value.
12.4.6.9
There are seven 64-bit context data registers that allow the host to read/write the contents of the context
used to process the message. The context must be written prior to the key data. If the context registers are
written during message processing, a context error will be generated. All context registers are cleared
when a hard/soft reset or initialization is performed.
The context registers must be read when changing context and restored to their original values to resume
processing an interrupted message (CBC, CTR and CCM modes). For CTR and CCM mode, all seven
64-bit context registers must be read to retrieve context, and all seven must be written back to restore
context. Effectively, the user must read the four empty place holder context registers in addition to the three
context registers holding the counter and counter modulus exponent when in CTR mode. The contents of
the empty context registers need not be preserved, but when restoring the CTR mode context, the ‘empty’
registers must be filled with 32 bytes of zeros before writing the saved counter and counter modulus
exponent.
Context should be loaded with the lower bytes in the lowest 64-bit context register. The context registers
are summarized in
Freescale Semiconductor
1
2
3
Address AESU 0x3_4050
Must be written at the start of a new message
Must be written at start of new CCM decryption
Header size/MAC size is only used if AES-CCM processing is suspended and resumed.
Reset
Cipher Mode
W
R
0
CCM
CBC
ECB
CTR
SRT
AESU Context Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IV1
Figure
—
—
1
IV
1
Counter
1
/MAC Tag
12-55.
1
IV2
—
—
2
1
Figure 12-55. AESU Context Register
Figure 12-54. AESU EU Go Register
Counter modulus
Encrypted MAC
exponent (M)
MAC/encrypted counter
—
—
—
3
Context Register (64 Bits Each)
1
AESU EU_Go
2
/decrypted
All zeros
—
—
—
—
4
—
—
—
5
Counter
Counter
1
1
—
—
—
6
Security Engine (SEC) 2.1
exponent
Counter modulus
Counter modulus
size/MAC size
Access: Write-only
exponent
—
—
—
7
1
/header
1
3
12-75
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