MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1073

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.4.2
The IP block revision register 2 is shown in
Table 18-14
18.3.5
18.3.5.1
The outbound address translation windows must be aligned based on the granularity selected by the size
fields. Outbound window misses use the default outbound register set (outbound ATMU window 0).
Overlapping outbound windows are not supported and will cause undefined behavior. Note that for RC
mode, all outbound transactions post ATMU must hit either into the memory base/limit range or the
prefetchable memory base/limit range defined in the PCI Express type 1 header. For EP mode, there is no
such requirement.
Note that in RC mode, there is no checking on whether the translated address actually hits into the memory
base/limit range. It will just pass it through as is.
Freescale Semiconductor
16–23
24–31
8–15
Bits
0–7
Offset 0xBFC
Reset
IP_CFG Block configuration option
IP_INT
Name
—
—
W
R
PCI Express ATMU Registers
contains descriptions of the fields of the IP block revision register 2.
IP Block Revision Register 2 (PEX_IP_BLK_REV2)
PCI Express Outbound ATMU Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Table 18-14. PCI Express IP Block Revision Register 2 Field Descriptions
Reserved
Block integration option
Reserved
Figure 18-12. IP Block Revision Register 2
7
8
IP_INT
Figure
18-12.
All zeros
15 16
Description
23 24
PCI Express Interface Controller
Access: Read-only
IP_CFG
31
18-19