MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1006

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

Offset 0xDB0, 0xDD0, 0xDF0

12–15 RTT Read transaction type. Transaction type to run if access is a read. The field description differs subject to

8–11 TRGT Target interface.

describes the fields of the PIWARn registers.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Enable. Enables this address translation

Prefetchable. Indicates that the address space is prefetchable so that prefetching and streaming are

0 Not prefetchable

1 Prefetchable

0100–1110 Reserved

Note: If this field is set to an I/O port rather than local memory space, attributes for the external I/O

transaction are assigned in an outbound ATMU of that I/O controller.

Note also that it is illegal for a PCI or PCI Express interface to use itself as a target.

the transaction being targeted to I/O interface or to local memory.

Following are the transaction type settings for reads to an I/O interface:

0000–0011 Reserved

0101–1111 Reserved

Following are the transaction type settings for reads to local memory:

0000–0011 Reserved

1000–1111 Reserved

Figure 17-14. PCI Inbound Window Attributes Registers

PCI Interface

PCI Express interface 2

PCI Express interface 1

PCI Express interface 3

Local Memory (DDR SDRAM, Local Bus, SRAM)

Read, don’t snoop local processor

Read, snoop local processor

Read, unlock L2 cache line

Table 17-14. PIWAR n Field Descriptions

Freescale Semiconductor

Access: Read/Write