MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1058
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Express Interface Controller
18.1.3
Several parameters that affect the PCI Express controller modes of operation are determined at power-on
reset (POR) by reset configuration signals as described in
18.1.3.1
The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) on the PCI
Express link. The host/agent configuration input signals cfg_host_agt[0:2] multiplexed on LWE/LBS[1:3]
determine the RC/EP mode.
18.1.3.2
The I/O port selection configuration input signals cfg_IO_ports[0:2] multiplexed on
TSEC3_TXD[6:4]determine the initial link width. (See
See
with regard to PCI Express link width selection.
18.2
Although the generic PCI Express controller described here accommodates up to a single x8 link, the three
PCI Express controller instantiations implemented on the MPC8544E offer either dual x4 links and a
single x1 link, or dual x2 links and a single x4 link. Please refer to
and the MPC8544EEC Electrical Characteristics document for specific pin muxing details.
18-4
•
•
•
•
•
•
•
•
•
Section 4.4.4.2.1, “Minimum Frequency Requirements,”
Host/Agent Configuration Selects between root complex (RC) and endpoint (EP) modes.
One virtual channel (VC0)
256-byte maximum payload size (MAX_PAYLOAD_SIZE)
Supports three inbound general-purpose translation windows and one configuration window
Supports four outbound translation windows and one default window
Supports eight non-posted and four posted PCI Express transactions
Supports up to six priority 0 internal platform reads and eight priority 0 to 2 internal platform
writes. (The maximum number of outstanding transactions at any given time is eight.)
Credit-based flow control management
Supports PCI Express messages and interrupts
Accepts up to 256-byte transactions from the internal platform (OCeaN)
I/O Port Selection
External Signal Descriptions
Modes of Operation
Parameter
Root Complex/Endpoint Modes
Link Width
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 18-1. POR Parameters for PCI Express Controller
Selects the width of the PCI Express link
Description
Section 4.4.3.6, “I/O Port
Chapter 4, “Reset, Clocking, and Initialization.”
for proper selection of CCB clock frequency
Section 4.4.3.6, “I/O Port
Selection.”)
Freescale Semiconductor
Section/Page
4.4.3.5/4-14
4.4.3.6/4-15
Selection,”
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