MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 205

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.8.2
All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.
5.8.3
The e500 core processes all interrupts as either machine check, critical, or noncritical types. Separate
control and status register sets are provided for each interrupt type. The core handles interrupts from these
three types in the following priority order:
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1. Machine check interrupt (highest priority)—The e500 defines a separate set of resources for the
2. Noncritical interrupts—First-level interrupts that allow the processor to change program flow to
3. Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or during regular
Asynchronous interrupts (such as machine check, critical input, and external interrupts) are caused
by events that are independent of instruction execution. For asynchronous interrupts, the address
reported in a save/restore register is the address of the instruction that would have executed next
had the asynchronous interrupt not occurred.
Synchronous interrupts are those that are caused directly by the execution or attempted execution
of instructions. Synchronous inputs may be either precise or imprecise, which are described as
follows:
— Synchronous precise interrupts are those that precisely indicate the address of the instruction
— Synchronous imprecise interrupts are those that may indicate the address of the instruction
machine check interrupt. They use the machine check save and restore registers
(MCSRR0/MCSRR1) to save state when they are taken, and they use the rfmci instruction to
restore state. These interrupts can be masked by the machine check enable bit, MSR[ME].
handle conditions generated by external signals, errors, or unusual conditions arising from program
execution or from programmable timer-related events. These interrupts are largely identical to
those previously defined by the OEA portion of the architecture. They use save and restore
registers (SRR0/SRR1) to save state when they are taken and they use the rfi instruction to restore
state. Asynchronous noncritical interrupts can be masked by the external interrupt enable bit,
MSR[EE].
program flow. They use the critical save and restore registers (CSRR0/CSRR1) to save state when
they are taken and they use the rfci instruction to restore state. These interrupts can be masked by
causing the exception that generated the interrupt or, in some cases, the address of the
immediately following instruction. The interrupt type and status bits indicate which instruction
is addressed in the appropriate save/restore register.
causing the exception that generated the interrupt or some instruction after the instruction
causing the interrupt. If the interrupt was caused by either the context synchronizing mechanism
or the execution synchronizing mechanism, the address in the appropriate save/restore register
is the address of the interrupt forcing instruction. If the interrupt was not caused by either of
those mechanisms, the address in the save/restore register is the last instruction to start execution
and may not have completed. No instruction following the instruction in the save/restore register
has executed.
Interrupt Classes
Interrupt Types
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Core Complex Overview
5-19