MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 764

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.6
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, TBIM, RPM, and RMM fields are read-only, having been set after sampling signals at
power-on-reset.
Figure 15-7
Table 15-10
15-32
Offset eTSEC1:0x2_4020; eTSEC3:0x2_5020
Reset
Reset
Bits
30
31
0–15
Bits
16
17
W
W
R
R FIFM
16
0
PERRDIS
DPEDIS
CLRCNT Clear all statistics counters
Name
Name
describes the definition for the ECNTRL register.
FIFM
CLRCNT AUTOZ STEN
describes the fields of the ECNTRL register.
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Ethernet Control Register (ECNTRL)
17
Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays.
Receive frame parse error disable.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
Reserved
FIFO mode enable. If this bit is set, 8-bit FIFO interface mode is enabled. This bit can be pin configured
at reset to set or clear. See
0 Interface to external signals via the Ethernet MAC.
1 Interface to external signals via the 8-bit FIFO interface, bypassing the Ethernet MAC. Frame parsing
0 Allow MIB counters to continue to increment.
1 Reset all MIB counters.
This bit is self-resetting.
in this mode automatically assumes that IP packets are being received and transmitted. See
FIFOCFG register for configuration of the FIFO interface.
18
Table 15-9. EDIS Field Descriptions (continued)
19
Figure 15-7. ECNTRL Register Definition
Table 15-10. ECNTRL Field Descriptions
20
Section 4.4.3, “Power-On Reset
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All zeros
All zeros
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24
Description
Description
GMIIM TBIM RPM
25
26
Configuration.”
27
R100M
28
Freescale Semiconductor
RMM SGMIIM
29
Access: Mixed
30
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15
31