MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 416

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
10.3.1
Most registers have one address. Some registers are replicated for each processor in a multiprocessor
device. In this case, each processor accesses its separate registers using the same address, the address
decoding being sensitive to the processor ID. A copy of the per-CPU registers is available to each
processor core at the same physical address, that is, the private access address space. The private access
address space acts like an alias to a processor’s own copy of the per-CPU registers. As shown in
Figure 10-42, the ID of the processor initiating the read/write transaction is used to determine which
processor’s per-CPU registers to access. For more information on per-CPU registers, see
“Per-CPU Registers.”
10.3.1.1
The block revision register (BRR1) shown in
10-18
0x6_0000–
0x6_0030
0x6_0040 IPIDR0—Interprocessor interrupt 0 (IPI 0) dispatch register
0x6_0050 IPIDR1—Interprocessor interrupt 1 (IPI 1) dispatch register
0x6_0060 IPIDR2—Interprocessor interrupt 2 (IPI 2) dispatch register
0x6_0070 IPIDR3—Interprocessor interrupt 3 (IPI 3) dispatch register
0x6_0080 CTPR—Current task priority register
0x6_0090 WHOAMI—Who am I register
0x6_00A0 IACK—interrupt acknowledge register
0x6_00B0 EOI—End of interrupt register
Offset 0x4_0000
Reset 0
Offset
W
R
0
Reserved
0
Global Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Register fields designated as write-1-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
Block Revision Register 1 (BRR1)
0
0
0
0
Table 10-6. PIC Register Address Map (continued)
0
IPID
Figure 10-3. Block Revision Register 1 (BRR1)
PIC Register Address Map—Per-CPU Registers
0
1
Register
0
0
0
Figure 10-3
0
NOTE
0
15 16
0
0
provides information about the IP block.
0
0
IPMJ
0
0
Access
0
R/W
—
W
W
R
R
1
23 24
0
0x0000_0000
0x0000_000F
0x0000_0000
0x0000_0000
0x0000_0000
0
Reset
Freescale Semiconductor
0
—
0
Access: Read only
Section 10.3.8,
IPMN
0
10.3.8.1/10-45
10.3.8.2/10-46
10.3.8.3/10-47
10.3.8.4/10-47
10.3.8.5/10-48
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