MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 667

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The LBC provides an SDRAM interface (machine) for the local bus. The machine provides the control

functions and signals for Intel PC133 and JEDEC-compliant SDRAM devices. Each bank can control an

SDRAM device on the local bus.

The memory controller supports any SDRAM configuration with the restrictions that all SDRAM devices

that reside on the bus should have the same port size and timing parameters (as defined in LSDMR).

Figure 14-34

lines. Note that address signals A[2:0] of the SDRAM connect directly to LA[27:29], address signal A10

connects to the LBCs dedicated LSDA10 signal, while the remaining address bits (except A10) are latched

from LAD[20:26].

Freescale Semiconductor

SDRAM Machine

shows an example connection between the LBC and a 32-bit SDRAM device with 12 address

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Supported SDRAM Configurations

Table 14-25. Boot Bank Field Values After Reset

0000_0000_0000_0000_0

From signal during reset.

0000_0000_0000_0000_0

Local Bus Controller