MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1152

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.4.1
This section describes some of the implementation details of the PCI Express controller.
18.4.1.1
Table 18-117
target.
18-98
PCI Express
Transaction
CfgRd0
CfgWr0
CfgRd1
CfgWr1
MRdLk
MsgD
IORd
IOWr
CplD
MWr
Msg
Mrd
Cpl
Architecture
Supported as
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Framing
PCI Express Transactions
Yes (RC only
contains the list of transactions that the PCI Express controller supports as an initiator and a
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
an Initiator
Yes
Yes
Yes
Yes
Yes
No
Sequence
Number
Supported as
Yes (EP only) Message Request with Data payload. Note that Set_Slot_Power_Limit is the
a Target
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Figure 18-124. PCI Express Packet Flow
Table 18-117. PCI Express Transactions
Header
Memory Read Request
Memory Read Lock. As a target, CplLk with UR status is returned.
Memory Write Request to memory-mapped PCI-Express space
I/O Read request. As a target, Cpl with UR status is returned
I/O Write Request. As a target, Cpl with UR status is returned
Configuration Read Type 0
Configuration Write Type 0
Configuration Read Type 1. As a target, Cpl with UR status is returned.
Configuration Write Type 1. As a target, Cpl with UR status is returned.
Message Request
only message with data that is supported and then only when the controller is
an initiator and in RC mode or a target and in EP mode.
Completion without Data
Completion with Data
Transaction Layer
Data Link Layer
Physical Layer
Data
ECRC
Definition
LCRC
Freescale Semiconductor
Framing