MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 187

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 5
Core Complex Overview
This chapter provides an overview of the e500 microprocessor core.
References to e500 are true for both the e500v1 and e500v2.
This chapter includes the following:
The e500 core provides features that the integrated device may not implement or may implement in a more
specific way.
5.1
The e500 core is a low-power implementation of the resources for embedded processors defined by the
Power ISA. The core is a 32-bit implementation using the lower words in the 64-bit general-purpose
registers (GPRs).
Figure 5-1
independently and in parallel. Note that this conceptual diagram does not attempt to show how these
features are physically implemented.
Freescale Semiconductor
An overview of architecture features as implemented in this core and a summary of the core feature
set
A summary of the instruction pipeline and flow
An overview of the programming model
An overview of interrupts and exception handling
A description of the memory management architecture
High-level details of the e500 core memory and coherency model
A brief description of the core complex bus (CCB)
A summary of the Power Architecture embedded category compatibility and migration from the
original version of the PowerPC™ architecture as it is defined by Apple, IBM, and Motorola
(referred to as the AIM version of the PowerPC architecture)
is a block diagram of the processor core complex that shows how the functional units operate
Overview
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
5-1

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