MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 383

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5.6
To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before using them
to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the DIMMs’
control bus by delaying the data and data mask writes (on SDRAM buses) by an extra SDRAM clock
cycle.
Figure 9-43
9.5.7
The DDR memory controller facilitates system design flexibility by providing a write timing adjustment
parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR
SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and
no later than 125% of a clock period—from the capturing clock edge of the command/address at the
SDRAM. The WR_DATA_DELAY parameter may be used to meet this timing requirement for a variety
of system configurations, ranging from a system with one DIMM to a fully populated system with two
DIMM. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The
delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.
Freescale Semiconductor
DDR SDRAM Registered DIMM Mode
DDR SDRAM Write Timing Adjustments
SDRAM Clock
shows the registered DDR SDRAM DIMM single-beat write timing.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MDM[0:7]
MDQS
MRAS
MCAS
MDQ n
MWE
MCS
MA n
Figure 9-43. Registered DDR SDRAM DIMM Burst Write Timing
ROW
0
1
ACTTORW
2
3
COL
4
5
COL
D0
6
D1 D2 D3
7
00
D0
8
D1 D2
9
D3
10
11
DDR Memory Controller
12
9-59