MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 76

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
14-22
14-23
14-24
14-25
14-26
14-27
14-28
14-29
14-30
14-31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
14-39
14-40
14-41
14-42
14-43
14-44
14-45
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
lxxvi
LCRR Field Descriptions.................................................................................................... 14-31
GPCM Write Control Signal Timing .................................................................................. 14-38
GPCM Read Control Signal Timing ................................................................................... 14-39
Boot Bank Field Values After Reset ................................................................................... 14-47
SDRAM Interface Commands ............................................................................................ 14-49
UPM Routines Start Addresses........................................................................................... 14-60
RAM Word Field Descriptions ........................................................................................... 14-65
MxMR Loop Field Use ....................................................................................................... 14-69
UPM Address Multiplexing ................................................................................................ 14-70
Data Bus Requirements For Read Cycle............................................................................. 14-84
Typical SDRAM Devices.................................................................................................... 14-86
LADn Signal Connections to 128-Mbyte SDRAM ............................................................ 14-88
Logical Address Bus Partitioning ....................................................................................... 14-89
SDRAM Device Address Port During Address Phase........................................................ 14-89
SDRAM Device Address Port During READ/WRITE Command..................................... 14-89
Register Settings for 128-Mbyte SDRAMs ........................................................................ 14-90
Logical Address Partitioning .............................................................................................. 14-90
SDRAM Device Address Port During Address Phase........................................................ 14-91
SDRAM Device Address Port During READ/WRITE Command..................................... 14-91
Register Settings for 512-Mbyte SDRAMs ........................................................................ 14-91
SDRAM Capacitance .......................................................................................................... 14-93
SDRAM AC Characteristics ............................................................................................... 14-94
Local Bus to MSC8101 HDI16 Connections...................................................................... 14-99
UPM Synchronization Cycles ........................................................................................... 14-107
eTSECn Network Interface Signal Properties ...................................................................... 15-7
eTSEC Signals—Detailed Signal Descriptions .................................................................... 15-9
Module Memory Map Summary......................................................................................... 15-13
Module Memory Map ......................................................................................................... 15-14
TSEC_ID Field Descriptions .............................................................................................. 15-23
TSEC_ID2 Field Descriptions ............................................................................................ 15-24
IEVENT Field Descriptions................................................................................................ 15-25
IMASK Field Descriptions ................................................................................................. 15-29
EDIS Field Descriptions ..................................................................................................... 15-31
ECNTRL Field Descriptions............................................................................................... 15-32
eTSEC Interface Configurations ......................................................................................... 15-34
PTV Field Descriptions ....................................................................................................... 15-35
DMACTRL Field Descriptions........................................................................................... 15-35
TBIPA Field Descriptions ................................................................................................... 15-37
TCTRL Field Descriptions.................................................................................................. 15-37
TSTAT Field Descriptions................................................................................................... 15-40
DFVLAN Field Descriptions .............................................................................................. 15-43
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
Title
Freescale Semiconductor
Number
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