MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 149

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
SD1_REF_CLK,
SD2_REF_CLK,
SD1_REF_CLK
SD2_REF_CLK
HRESET_REQ
LSSD_MODE
SD1_RX[7:4],
SD1_TX[3:0],
SD1_TX[7:4],
SD2_RX[3:2],
SD2_TX[3:2],
CKSTP_OUT
MSRCID[2:4]
SD1_RX[7:4]
SD1_TX[3:0]
SD1_TX[7:4]
SD2_RX[3:2]
SD2_TX[3:2]
GPOUT[0:7]
L1_TSTCLK
SD2_RX[0],
SD2_TX[0],
SD2_RX[0]
TRIG_OUT
SD2_TX[0]
CKSTP_IN
MSRCID0
MSRCID1
GPIN[0:7]
HRESET
SRESET
TRIG_IN
ASLEEP
READY
MDVAL
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 3-1. MPC8544E Signal Reference by Functional Block (continued)
Receive data,
receive data complement
Transmit data,
transmit data complement
Transmit data,
transmit data complement
SerDes1 reference clock,
SerDes1 reference clock
complement
Receive data,
receive data complement
Receive data,
receive data complement
Transmit data,
transmit data complement
Transmit data,
transmit data complement
SerDes2 reference clock,
SerDes2 reference clock
complement
Hard reset
Hard reset request
Soft reset
Checkstop in
Checkstop out
General-purpose output
General-purpose input
Device ready
Asleep
Watchpoint trigger in
Watchpoint trigger out
Memory debug source port ID 0
Memory debug source port ID 1
Memory debug source port ID
2–4
Memory debug data valid
LSSD mode
L1 test clock
Description
purpose outputs
PCI Express 1,
PCI Express 3,
System control
System control
System control
System control
System control
purpose inputs
System control
PCI Express 2
PCI Express 1
PCI Express 2
PCI Express 2
PCI Express 3
PCI Express 3
Power mgmt
Functional
General-
General-
Debug
Debug
Debug
Debug
Debug
Debug
Block
SGMII
SGMII
SGMII
Test
Test
Alternate Function(s)
cfg_mem_debug
cfg_ddr_debug
TRIG_OUT
READY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signals
No. of
8
8
8
2
4
4
4
4
2
1
1
1
1
1
8
8
1
1
1
1
1
1
3
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Signal Descriptions
19.4.1.9/19-12
19.4.1.9/19-12
19-2/19-2
19-2/19-2
19-2/19-2
19-2/19-2
19-2/19-2
21-4/21-8
21-4/21-8
21-3/21-7
21-3/21-7
21-3/21-7
21-3/21-7
21-5/21-8
21-5/21-8
4-2/4-2
4-2/4-2
4-2/4-2
4-2/4-2
Table/
Page
3-9