MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 481

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12
Security Engine (SEC) 2.1
This chapter describes the functionality of the integrated security engine (SEC 2.1) of the MPC8544E. It
addresses the following topics:
The SEC 2.1 is designed to off-load computationally intensive security functions, such as key generation
and exchange, authentication, and bulk encryption from the processor core of the MPC8544E. It is
optimized to process all the algorithms associated with IPSec, IKE, SSL/TLS, iSCSI, SRTP, and 802.11i.
The SEC 2.1 is derived from integrated security cores found in other members of the PowerQUICC family,
including the SEC 2.0, the version implemented in the MPC8555E and MPC8541E.
The security engine’s execution units (EUs) and primary features include the following:
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Section 12.1, “SEC 2.1 Architecture Overview”
Section 12.2, “Configuration of Internal Memory Space”
Section 12.3, “Descriptor Overview”
Section 12.4, “Execution Units”
Section 12.5, “Crypto-Channels”
Section 12.6, “Security Controller”
Section 12.7, “Power-Saving Mode”
PKEU—Public key execution unit that supports the following:
— RSA (Rivest-Shamir-Adleman) and Diffie-Hellman algorithms
— Elliptic curve cryptography
DEU—Data encryption standard execution unit
— DES, 3DES
— Two key (K1, K2, K1) or three key (K1, K2, K3)
— ECB and CBC modes for both DES and 3DES
AESU—Advanced encryption standard unit
— Implements the Rijndael symmetric-key cipher
— ECB, CBC, CCM, and counter modes
— 128-, 192-, 256-bit key lengths
– Programmable field size up to 2048 bits
– F
– Programmable field size up to 511 bits
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
m and F(p) modes
12-1