IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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INSTRUCTION SET (Cont’d)
Conditional Branch. Branch instructions perform
a branch in the program when the selected condi-
tion is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in Data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Table 19. Conditional Branch Instructions
Instruction
Branch If
JRC e
C = 1
JRNC e
C = 0
JRZ e
Z = 1
JRNZ e
Z = 0
JRR b, rr, ee
Bit = 0
JRS b, rr, ee
Bit = 1
:
Notes
b
3-bit address
e
5 bit signed displacement in the range -15 to +16
ee
8 bit signed displacement in the range -126 to +129
Table 20. Bit Manipulation Instructions
Instruction
Addressing Mode
SET b,rr
Bit Direct
RES b,rr
Bit Direct
Notes:
b
3-bit address
rr
Data space register
Bit Manipulation Instructions should not be used on Port Data Registers and any registers with read only and/or write only bits (see I/O port
chapter)
Table 21. Control Instructions
Instruction
Addressing Mode
NOP
Inherent
RET
Inherent
RETI
Inherent
(1)
STOP
Inherent
WAIT
Inherent
Notes:
1.
This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
Δ
Affected
Table 22. Jump & Call Instructions
Instruction
Addressing Mode
CALL abc
Extended
JP abc
Extended
Notes:
abc 12-bit address
*
Not Affected
ST6208C/ST6209C/ST6210C/ST6220C
Control Instructions. Control instructions control
microcontroller operations during program execu-
tion.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutine calls
to any location in the whole program space.
Bytes
Cycles
1
2
1
2
1
2
1
2
3
5
3
5
rr
Data space register
Δ
Affected. The tested bit is shifted into carry.
*
Not Affected
Bytes
Cycles
2
4
2
4
*
Not Affected
Bytes
Cycles
1
2
1
2
1
2
1
2
1
2
*Not Affected
Bytes
Cycles
2
4
2
4
Flags
Z
C
*
*
*
*
*
*
*
*
Δ
*
Δ
*
Flags
Z
C
*
*
*
*
Flags
Z
C
*
*
*
*
Δ
Δ
*
*
*
*
Flags
Z
C
*
*
*
*
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