IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 

Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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ST6208C/ST6209C/ST6210C/ST6220C
8-BIT TIMER (Cont’d)
8.2.4 Functional Description
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
÷ 12 or TIMER pin signal), and to
INT
the output mode.
The settings for the different operating modes are
summarized
Table
13.
Table 13. Timer Operating Modes
Timer
TOUT DOUT
Function
Event Counter
External counter clock
0
0
(input)
Gated input
External Pulse length
0
1
(input)
Output “0”
1
0
(output)
Output “1”
1
1
(output)
8.2.4.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this mode, the prescaler is decremented by the
Timer clock input, but only when the signal on the
TIMER pin is held high (f
/12 gated by TIMER
INT
pin). See
Figure 28
and
Figure
This mode is selected by clearing the TOUT bit in
the TSCR register (i.e. as input) and setting the
DOUT bit.
Note: In this mode, if the TIMER pin is multi-
plexed, the corresponding port control bits have to
be set in input with pull-up configuration through
48/104
1
the DDR, OR and DR registers. For more details,
please refer to the I/O Ports section.
Figure 28. f
TIMER
Figure 29. Gated Mode Operation
Application
COUNTER VALUE
xx1
source
measurement
xx2
Output signal
generation
TIMER PIN
1
29.
TIMER CLOCK
Clock in Gated Mode
TIMER
f
/12
INT
f
PRESCALER
f
EXT
VALUE 1
VALUE 2
PULSE LENGTH