IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part NumberST62T20CB6
DescriptionIC MCU 8BIT OTP 4K 20 PDIP
ManufacturerSTMicroelectronics
SeriesST6
ST62T20CB6 datasheet
 


Specifications of ST62T20CB6

Core ProcessorST6Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, WDT
Number Of I /o12Program Memory Size4KB (4K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 6 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case20-DIP (0.300", 7.62mm)Controller Family/seriesST6
No. Of I/o's12Ram Memory Size64Byte
Cpu Speed8MHzNo. Of Timers1
Rohs CompliantYesProcessor SeriesST62T2x
CoreST6Data Bus Width8 bit
Data Ram Size64 BMaximum Clock Frequency8 MHz
Number Of Programmable I/os12Number Of Timers2
Operating Supply Voltage3 V to 6 VMaximum Operating Temperature+ 85 C
Mounting StyleThrough HoleDevelopment Tools By SupplierST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature- 40 COn-chip Adc8 bit
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Connectivity-Other names497-2098-5
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10.9 CONTROL PIN CHARACTERISTICS
10.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Symbol
Parameter
V
Input low level voltage
IL
V
Input high level voltage
IH
V
Schmitt trigger voltage hysteresis
hys
R
Weak pull-up equivalent resistor
ON
R
ESD resistor protection
ESD
t
Generated reset pulse duration
w(RSTL)out
t
External reset pulse hold time
h(RSTL)in
t
Filtered glitch duration
g(RSTL)in
Notes:
1. Unless otherwise specified, typical data are based on T
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R
pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
ON
not tested in production.
5. All short pulse applied on RESET pin with a duration below t
6. The reset network protects the device against parasitic resets, especially in a noisy environment.
7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device
can be damaged when the ST6 generates an internal reset (LVD or watchdog).
Figure 69. Typical R
vs V
ON
DD
Ron [Kohm]
1000
900
800
700
600
500
400
300
200
100
ST6208C/ST6209C/ST6210C/ST6220C
, f
, and T
DD
OSC
A
Conditions
2)
2)
3)
V
=5V
=
DD
4)
V
V
IN
SS
V
=3.3V
DD
V
=5V
=
DD
V
V
IN
SS
V
=3.3V
DD
External pin or
internal reset sources
5)
6)
=25°C and V
A
h(RSTL)in
with V
=V
IN
SS
Ta=-40°C
Ta=25°C
3
4
VDD [V]
unless otherwise specified.
1)
Min
Typ
Max
0.3xV
0.7xV
DD
200
400
150
350
900
300
730
1900
2.8
=5V.
DD
can be ignored.
Ta=95°C
Ta=125°C
5
6
Unit
DD
V
mV
t
CPU
μs
μs
ns
85/104
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