C8051T611-GM Silicon Laboratories Inc, C8051T611-GM Datasheet - Page 101

IC 8051 MCU 16K BYTE-PROG 28-QFN

C8051T611-GM

Manufacturer Part Number
C8051T611-GM
Description
IC 8051 MCU 16K BYTE-PROG 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Datasheets

Specifications of C8051T611-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 21 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1436-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T611-GM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051T611-GMR
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
C8051T611-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
19.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on or V
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
is enabled following a power-on reset.
Logic HIGH
RST
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
ramp time is defined as how fast V
RST
Figure 19.2. Power-On and V
monitor event timing. The maximum V
V
RST
DD
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
Power-On
PORDelay
Reset
T
) is typically less than 0.3 ms.
PORDelay
Rev 1.0
DD
DD
DD
C8051T610/1/2/3/4/5/6/7
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
RST
Monitor
Reset
VDD
level. For ramp times less than
RST
). Figure 19.2. plots the
DD
settles above
DD
VDD
DD
ramp time
monitor
101
t

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