C8051T611-GM Silicon Laboratories Inc, C8051T611-GM Datasheet - Page 113

• Manufacturer Part Number: C8051T611-GM
• Description: IC 8051 MCU 16K BYTE-PROG 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T611-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 21 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1436-5

21. Port Input/Output
Digital and analog resources are available through 29 I/O pins organized as three byte-wide ports and one
5-bit-wide port on the C8051T610/2/4. The C8051T611/3/5 devices have 25 I/O pins available, organized
as three byte-wide ports and one 1-bit-wide port. The C8051T616/7 have 21 I/O pins available on a single
byte-wide port, two 6-bit-wide ports, and a 1-bit-wide port.
Port pins can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources,
or assigned to an analog function as shown in Figure 21.3. Port pin P3.0 is shared with the C2 Interface
Data signal (C2D). The designer has complete control over which functions are assigned, limited only by
the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Prior-
ity Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port
latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 21.3, Figure 21.4, and Figure 21.5). The registers XBR0 and XBR1, defined in SFR Definition 21.1
and SFR Definition 21.2, are used to select internal digital functions.
All Port I/O pins are 5 V tolerant (refer to Figure 21.2 for the Port cell circuit). The Port I/O cells are config-
ured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3).
Complete Electrical Specifications for Port I/O are given in Table 7.3 on page 33.
Highest
Priority
Lowest
Priority
Figure 21.1. Port I/O Functional Block Diagram
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
CP0,
CP1
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.3)
(P2.4-P2.7)
(P3.0-P3.4)
2
4
2
4
6
2
8
8
4
4
5
Rev 1.0
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
PnSKIP
Digital
C8051T610/1/2/3/4/5/6/7
EX0 and EX1
8
8
4
Interrupts
External
4
5
PnMDOUT,
Registers
PnMDIN
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
P0
P1
P2
P3
Peripherals
To Analog
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
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