C8051T611-GM Silicon Laboratories Inc, C8051T611-GM Datasheet - Page 58

• Manufacturer Part Number: C8051T611-GM
• Description: IC 8051 MCU 16K BYTE-PROG 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T611-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 21 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1436-5

C8051T610/1/2/3/4/5/6/7
12. Comparator0 and Comparator1
C8051T610/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators: Comparator0 is
shown in Figure 12.1, Comparator1 is shown in Figure 12.2. The two comparators operate identically with
the following exceptions: (1) Their input selections differ as described in Section “12.1. Comparator Multi-
plexers” on page 65; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the sys-
tem clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “21.4. Port I/O Initialization” on page 121). Comparator0 may also be used as a
reset source (see Section “19.5. Comparator0 Reset” on page 104).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“12.1. Comparator Multiplexers” on page 65.
58
Comparator
Input Mux
Figure 12.1. Comparator0 Functional Block Diagram
CPT0MD
CP0 +
CP0 -
+
-
CPT0CN
VDD
GND
CP0RIF
CP0FIF
Decision
Reset
Tree
Rev 1.0
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
Crossbar
0
1
EA
0
1
CP0A
Interrupt
CP0
CP0