C8051T611-GM Silicon Laboratories Inc, C8051T611-GM Datasheet - Page 215

IC 8051 MCU 16K BYTE-PROG 28-QFN

C8051T611-GM

Manufacturer Part Number
C8051T611-GM
Description
IC 8051 MCU 16K BYTE-PROG 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Datasheets

Specifications of C8051T611-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 21 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1436-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T611-GM
Manufacturer:
Silicon Labs
Quantity:
135
Part Number:
C8051T611-GMR
Manufacturer:
SILICON
Quantity:
3 500
Part Number:
C8051T611-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
EPROM programming functions may be performed. This is possible because C2 communication is typi-
cally performed when the device is in the halt state, where all on-chip peripherals and user software are
stalled. In this halted state, the C2 interface can safely ‘borrow’ the C2CK (normally RST) and C2D pins. In
most applications, external resistors are required to isolate C2 interface traffic from the user application
when performing debug functions. These external resistors are not necessary for production boards. A typ-
ical isolation configuration is shown in Figure 27.1.
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
/Reset (a)
Output (c)
Input (b)
Figure 27.1. Typical C2 Pin Sharing
C2 Interface Master
Rev 1.0
C8051T610/1/2/3/4/5/6/7
C2CK
C2D
215

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