C8051T611-GM Silicon Laboratories Inc, C8051T611-GM Datasheet - Page 204

• Manufacturer Part Number: C8051T611-GM
• Description: IC 8051 MCU 16K BYTE-PROG 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T611-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 21 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1436-5

C8051T610/1/2/3/4/5/6/7
SFR Definition 26.2. PCA0MD: PCA Mode
SFR Address = 0xD9
204
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
Name
Reset
3:1
Bit
Type
7
6
5
4
0
Bit
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
CPS[2:0] PCA Counter/Timer Pulse Select.
WDLCK
Unused
WDTE
Name
CIDL
ECF
CIDL
R/W
7
0
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Watchdog Timer Enable.
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Unused. Read = 0b, Write = Don't care.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
WDTE
R/W
6
1
WDLCK
R/W
5
0
Rev 1.0
R
4
0
Function
3
0
CPS[2:0]
R/W
2
0
1
0
ECF
R/W
0
0