MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 106

• Manufacturer Part Number: MCR908JK1ECPE
• Description: IC MCU 1.5K FLASH 8MHZ 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK1ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 14
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Input/Output (I/O) Ports
10.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a one to a
DDRA bit enables the output buffer for the corresponding port A pin; a zero disables the output buffer.
DDRA[6:0] — Data Direction Register A Bits
Figure 10-4
When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading
address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the
state of its data direction bit.
106
These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
Address:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
$0004
Bit 7
0
0
Figure 10-3. Data Direction Register A (DDRA)
RESET
= Unimplemented
DDRA6
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
Figure 10-4. Port A I/O Circuit
DDRA5
5
0
DDRAx
PTAx
NOTE
DDRA4
4
0
DDRA3
3
0
PTAPUEx
DDRA2
2
0
DDRA1
To Keyboard Interrupt Circuit
30k
1
0
PTAx
Freescale Semiconductor
DDRA0
Bit 0
0