MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 25

• Manufacturer Part Number: MCR908JK1ECPE
• Description: IC MCU 1.5K FLASH 8MHZ 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK1ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 14
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Note: Writing a 0 clears SBSW.
$003C
$003D
$FE00
$FE01
$FE02
$FE03
$0027
$0028
$0029
$002A
$002B
$003B
$003E
$003F
Addr.
↓
TIM Channel 1 Register High
TIM Channel 0 Register Low
TIM Channel 1 Register Low
TIM Channel 1 Status and
ADC Input Clock Register
Control Register (TSC1)
ADC Status and Control
Register Name
Break Status Register
Reset Status Register
ADC Data Register
Break Flag Control
Register (ADSCR)
Register (BFCR)
Unimplemented
Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 4)
(ADICLK)
Reserved
(TCH1H)
(TCH0L)
(TCH1L)
(ADR)
(BSR)
(RSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
MC68HC908JL3E Family Data Sheet, Rev. 4
COCO
ADIV2
CH1F
BCFE
Bit15
Bit 7
POR
AD7
Bit7
Bit7
R
R
0
0
0
0
1
0
= Unimplemented
CH1IE
ADIV1
Bit14
AIEN
AD6
Bit6
Bit6
PIN
R
R
R
6
0
0
0
0
ADCO
ADIV0
Bit13
COP
AD5
Bit5
Bit5
R
R
R
5
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
ADCH4
MS1A
Bit12
ILOP
AD4
Bit4
Bit4
R
R
R
4
0
1
0
0
0
ADCH3
ELS1B
Bit11
ILAD
AD3
Bit3
Bit3
R
R
R
R
3
0
1
0
0
0
= Reserved
MODRST
ADCH2
ELS1A
Bit10
AD2
Bit2
Bit2
R
R
R
2
0
1
0
0
0
See note
ADCH1
SBSW
TOV1
AD1
Bit1
Bit9
Bit1
LVI
R
R
1
0
1
0
0
0
0
Monitor ROM
CH1MAX
ADCH0
Bit 0
AD0
Bit0
Bit8
Bit0
R
R
R
0
1
0
0
0
0
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