MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 141

• Manufacturer Part Number: MCR908JK1ECPE
• Description: IC MCU 1.5K FLASH 8MHZ 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK1ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 14
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

16.9 3V Control Timing
Freescale Semiconductor
LVI reset voltage
Internal operating frequency
RST input pulse width low
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. Stop I
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
8. R
1. V
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
loads. Less than 100 pF on all outputs. C
affects run I
than 100 pF on all outputs. C
V
noted.
mation.
DD
DD
DD
PU1
= 2.7 to 3.3 Vdc, V
= 2.7 to 3.3 Vdc, V
is reached.
and R
DD
DD
measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
measured using external square wave clock source (f
PU2
DD
DD
. Measured with all modules enabled.
are measured at V
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
Characteristic
DD
measured using external square wave clock source (f
Table 16-7. DC Electrical Characteristics (3V) (Continued)
(3)
Characteristic
SS
SS
(2)
= 0 Vdc, T
= 0 Vdc, T
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
(1)
DD
MC68HC908JL3E Family Data Sheet, Rev. 4
A
A
= 5.0V.
(1)
= T
= T
Table 16-8. Control Timing (3V)
L
L
L
to T
to T
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
H
H
; timing shown with respect to 20% V
, unless otherwise noted.
Symbol
V
LVR3
OP
= 2MHz). All inputs 0.2V from rail. No dc loads. Less
Symbol
t
f
IRL
OP
OP
Min
2.0
= 2MHz). All inputs 0.2V from rail. No dc
DD
Min
1.5
—
and 70% V
Typ
2.4
(2)
Max
DD
—
4
3V Control Timing
, unless otherwise
Max
2.69
MHz
Unit
μs
Unit
V
DD
141
.