MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 116

• Manufacturer Part Number: MCR908JK1ECPE
• Description: IC MCU 1.5K FLASH 8MHZ 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK1ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 14
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

External Interrupt (IRQ)
11.5 IRQ Status and Control Register (INTSCR)
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR has the following functions:
IRQF — IRQ Flag
ACK — IRQ Interrupt Request Acknowledge Bit
IMASK — IRQ Interrupt Mask Bit
MODE — IRQ Edge/Level Select Bit
IRQPUD — IRQ Pin Pull-up control bit
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This read-only status bit is high when the IRQ interrupt is pending.
Writing a one to this write-only bit clears the IRQ latch. ACK always reads as zero. Reset clears ACK.
Writing a one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and V
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ and interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
POR:
IRQPUD
Figure 11-3. IRQ Status and Control Register (INTSCR)
$001D
$001E
Bit 7
Bit 7
R
0
0
0
0
Figure 11-4. Configuration Register 2 (CONFIG2)
= Unimplemented
= Reserved
MC68HC908JL3E Family Data Sheet, Rev. 4
R
6
0
0
6
0
0
R
5
0
0
5
0
0
Not affected Not affected
LVIT1
4
0
0
4
0
LVIT0
IRQF
3
0
3
0
DD
ACK
R
2
0
2
0
0
IMASK
R
1
0
1
0
0
Freescale Semiconductor
MODE
Bit 0
Bit 0
R
0
0
0