MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 112

IC MCU 1.5K FLASH 8MHZ 20-DIP

MCR908JK1ECPE

Manufacturer Part Number
MCR908JK1ECPE
Description
IC MCU 1.5K FLASH 8MHZ 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCR908JK1ECPE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
14
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
HC08JK
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCR908JK1ECPE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Input/Output (I/O) Ports
10.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
SLOWDx — Slow Edge Enable
PTDPUx — Pull-up Enable
112
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
The PTDPU6 and PTDPU7 bits enable the 5kΩ pull-up on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
1 = Enable 5kΩ pull-up
0 = Disable 5kΩ pull-up
Address:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Reset:
Read:
Write:
DDRD
Bit
0
1
$000A
Bit 7
0
0
PTD Bit
Figure 10-12. Port D Control Register (PDCR)
X
X
= Unimplemented
(1)
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
0
Table 10-4. Port D Pin Functions
I/O Pin Mode
Input, Hi-Z
Output
5
0
0
(2)
4
0
0
Accesses to
Read/Write
DDRD[7:0]
DDRD[7:0]
DDRD
SLOWD7
3
0
SLOWD6
Read
2
0
Pin
Pin
Accesses to PTD
PTDPU7
1
0
PTD[7:0]
PTD[7:0]
Write
Freescale Semiconductor
PTDPU6
Bit 0
(3)
0

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