MCR908JK1ECPE Freescale Semiconductor, MCR908JK1ECPE Datasheet - Page 93

• Manufacturer Part Number: MCR908JK1ECPE
• Description: IC MCU 1.5K FLASH 8MHZ 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK1ECPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 14
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
ELSxB and ELSxA — Edge/Level Select Bits
Freescale Semiconductor
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register. Setting MS0B disables the channel 1 status and control register
and reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation. See
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See
Table
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel
x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel
x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
MSxB
8-3.) Reset clears the MSxA bit.
X
X
0
0
0
0
0
0
1
1
1
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
MSxA
X
X
X
0
1
0
0
0
1
1
1
ELSxB
0
0
0
1
1
0
1
1
0
1
1
Table 8-3. Mode, Edge, and Level Selection
MC68HC908JL3E Family Data Sheet, Rev. 4
ELSxA
0
0
1
0
1
1
0
1
1
0
1
Table
Buffered Output
Output Preset
Input Capture
Compare or
Compare or
Buffered
Output
8-3.
Mode
PWM
PWM
NOTE
NOTE
Pin under Port Control; Initial Output Level High
Pin under Port Control; Initial Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Configuration
I/O Registers
Table 8-3
93