UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet
UPD70F3786GJ-GAE-AX
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UPD70F3786GJ-GAE-AX Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual V850ES/JH3-E, V850ES/JJ3-E 32-bit Single-Chip Microcontrollers Hardware V850ES/JH3-E μ PD70F3778 μ PD70F3779 μ PD70F3780 μ PD70F3781 μ PD70F3782 μ PD70F3783 Document No. U19601EJ2V0UD00 (2nd edition) Date Published September 2009 NS 2009 Printed in Japan V850ES/JJ3-E μ PD70F3784 μ PD70F3785 ...
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User’s Manual U19601EJ2V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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Caution: This product uses SuperFlash EEPROM is a trademark of NEC Electronics Corporation. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or ...
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The information in this document is current as of September, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for the most up-to-date specifications of ...
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Readers This manual is intended for users who wish to understand the functions of the V850ES/JH3-E and V850ES/JJ3-E and design application systems using the V850ES/JH3-E and V850ES/JJ3-E. Purpose This manual is intended to give users an understanding of the hardware ...
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Conventions Data significance: Active low representation: Memory map address: Note: Caution: Remark: Numeric representation: Prefix indicating power of 2 (address space, memory capacity): Higher digits on the left and lower digits on the right xxx (overscore over pin or signal ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JH3-E and V850ES/JJ3-E V850ES Architecture User’s Manual V850ES/JH3-E, V850ES/JJ3-E Hardware User’s Manual Documents related to development ...
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CHAPTER 1 INTRODUCTION .................................................................................................................24 1.1 General.......................................................................................................................................24 1.2 Features .....................................................................................................................................27 1.3 Application Fields .....................................................................................................................29 1.4 Ordering Information ................................................................................................................29 1.5 Pin Configuration (Top View)...................................................................................................30 1.6 Function Block Configuration .................................................................................................33 1.6.1 Internal block diagram ................................................................................................................. 33 1.6.2 Internal units................................................................................................................................ 35 CHAPTER 2 PIN ...
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Port 7.........................................................................................................................................148 4.3.7 Port 9.........................................................................................................................................151 4.3.8 Port CM .....................................................................................................................................160 4.3.9 Port CS......................................................................................................................................163 4.3.10 Port CT ......................................................................................................................................166 4.3.11 Port DH......................................................................................................................................168 4.3.12 Port DL ......................................................................................................................................175 4.4 Port Register Settings When Alternate Function Is Used...................................................177 4.5 Cautions ...................................................................................................................................191 4.5.1 Cautions on setting ...
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Registers ................................................................................................................................... 228 6.5.3 Usage........................................................................................................................................ 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA) ..............................................................232 7.1 Overview ..................................................................................................................................232 7.2 Functions .................................................................................................................................232 7.3 Configuration ..........................................................................................................................233 7.3.1 Pin configuration........................................................................................................................ 235 7.4 Registers..................................................................................................................................236 7.5 Operation .................................................................................................................................253 7.5.1 Interval timer mode (TAAnMD2 to TAAnMD0 ...
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Configuration...........................................................................................................................454 9.3.1 Pin configuration........................................................................................................................457 9.4 Registers ..................................................................................................................................458 9.5 Timer Output Operations........................................................................................................479 9.6 Operation .................................................................................................................................480 9.6.1 Interval timer mode (TT0MD3 to TT0MD0 bits = 0000) .............................................................488 9.6.2 External event count mode (TT0MD3 to TT0MD0 bits = 0001) .................................................498 9.6.3 External ...
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Initial INTRTC2 interrupt settings .............................................................................................. 679 12.4.7 Changing INTRTC2 interrupt setting during clock operation ..................................................... 680 12.4.8 Initializing real-time counter....................................................................................................... 681 12.4.9 Watch error correction example of real-time counter................................................................. 682 CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2....................................................................686 13.1 Functions ...
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Reception error..........................................................................................................................773 16.7.6 Parity types and corresponding operation .................................................................................774 16.7.7 Receive data noise filter ............................................................................................................775 16.8 Dedicated Baud Rate Generator (BRG) ................................................................................776 16.9 Control Flow ............................................................................................................................782 16.10 Cautions ...................................................................................................................................793 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 795 17.1 ...
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CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF) ................................................................889 19.1 Features ...................................................................................................................................889 19.2 Configuration ..........................................................................................................................890 19.3 Mode Switching Between CSIF and Other Serial Interfaces ..............................................891 19.3.1 Switching between CSIF0, UARTC3, and I 19.3.2 Mode switching between CSIF1, UARTC1, and I 19.3.3 ...
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ACK ...........................................................................................................................................975 20.6.5 Stop condition............................................................................................................................976 20.6.6 Wait state ..................................................................................................................................977 20.6.7 Wait state cancellation method..................................................................................................979 2 20 Interrupt Request Signals (INTIICn).................................................................................980 20.7.1 Master device operation ............................................................................................................980 20.7.2 Slave device operation (when receiving slave address data (address match))..........................983 20.7.3 ...
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CAN controller configuration.................................................................................................... 1054 21.5.2 Register access type ............................................................................................................... 1055 21.5.3 Register bit configuration......................................................................................................... 1072 21.6 Registers................................................................................................................................1076 21.7 Bit Set/Clear Function ..........................................................................................................1112 21.8 CAN Controller Initialization ................................................................................................1114 21.8.1 Initialization of CAN module .................................................................................................... 1114 21.8.2 Initialization of message buffer ...
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Connection configuration .........................................................................................................1182 22.4 Cautions ................................................................................................................................ 1184 22.5 Requests ............................................................................................................................... 1185 22.5.1 Automatic requests..................................................................................................................1185 22.5.2 Other requests.........................................................................................................................1192 22.6 Register Configuration ........................................................................................................ 1193 22.6.1 USB control registers...............................................................................................................1193 22.6.2 USB function controller register list..........................................................................................1194 22.6.3 EPC control registers...............................................................................................................1210 22.6.4 Data hold ...
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Descriptor mechanism............................................................................................................. 1505 23.6.3 Frame transmission................................................................................................................. 1514 23.6.4 Frame reception ...................................................................................................................... 1519 23.6.5 Error occurrence...................................................................................................................... 1524 23.7 Receive Checksum ...............................................................................................................1525 23.7.1 Processing by software ........................................................................................................... 1525 23.8 Notes ........................................................................................................................................1527 23.8.1 Notes on FIFO......................................................................................................................... 1527 CHAPTER 24 DMA FUNCTION (DMA ...
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Edge detection.........................................................................................................................1593 25.7 Interrupt Acknowledge Time of CPU.................................................................................. 1601 25.8 Periods in Which Interrupts Are Not Acknowledged by CPU.......................................... 1602 25.9 Cautions ................................................................................................................................ 1602 CHAPTER 26 KEY INTERRUPT FUNCTION ................................................................................... 1603 26.1 Function ................................................................................................................................ 1603 26.2 Register ................................................................................................................................. 1604 ...
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Configuration ........................................................................................................................1638 29.3 Register..................................................................................................................................1639 29.4 Operation ...............................................................................................................................1640 CHAPTER 30 LOW-VOLTAGE DETECTOR (LVI)............................................................................1643 30.1 Functions ...............................................................................................................................1643 30.2 Configuration ........................................................................................................................1643 30.3 Registers................................................................................................................................1644 30.4 Operation ...............................................................................................................................1646 30.4.1 To use for internal reset signal ................................................................................................ 1646 30.4.2 To use for interrupt .................................................................................................................. 1647 ...
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Connection circuit example......................................................................................................1687 34.1.2 Interface signals ......................................................................................................................1687 34.1.3 Maskable functions..................................................................................................................1689 34.1.4 Register ...................................................................................................................................1689 34.1.5 Operation.................................................................................................................................1691 34.1.6 Cautions ..................................................................................................................................1691 34.2 Debugging Without Using DCU .......................................................................................... 1692 34.2.1 Circuit connection examples....................................................................................................1692 34.2.2 Maskable functions..................................................................................................................1695 34.2.3 Securement of user resources.................................................................................................1696 34.2.4 Cautions ...
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A.6 Embedded Software .............................................................................................................1759 A.7 Flash Memory Writing Tools................................................................................................1759 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/Jx3-E AND V850ES/Jx3-H.............1760 APPENDIX C REGISTER INDEX........................................................................................................1761 APPENDIX D INSTRUCTION SET LIST............................................................................................1804 D.1 Conventions ..........................................................................................................................1804 D.2 Instruction Set (in Alphabetical Order)...............................................................................1807 APPENDIX E REVISION HISTORY .....................................................................................................1814 ...
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The V850ES/JH3-E and V850ES/JJ3-E are products in the low-power series of NEC Electronics’ V850 single-chip microcontrollers designed for real-time control applications. 1.1 General The V850ES/JH3-E and V850ES/JJ3-E are 32-bit single-chip microcontrollers that use the V850ES CPU core and incorporate peripheral ...
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Generic Name μ Part Number PD70F3778 Internal Flash memory 256 KB memory Internal RAM 60 KB Data-only RAM 16 KB Memory Logical space 64 MB space External memory area 5 MB External bus interface Address bus: 22, Address/data bus: 16 ...
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Generic Name Part Number Internal Flash memory memory Internal RAM Data-only RAM Memory Logical space 64 MB space External memory area 13 MB External bus interface Address bus: 24, Address/data bus: 16 Separate bus/Multiplexed bus 32 bits × 32 registers ...
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Features Minimum instruction execution time: 20.0 ns (main clock (f 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32 clocks CPU features: Signed multiplication (32 × 32 → 64 ...
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Real-time counter (RTC): Watchdog timer: 6 bits × 1 channel Real-time output port: Serial interface: Asynchronous serial interface B with FIFO (UARTB) Asynchronous serial interface C (UARTC) 3-wire variable-length serial interface E with FIFO (CSIE) 3-wire variable-length serial interface F ...
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Application Fields Equipment requiring an Ethernet controller, industrial equipment, FA equipment, network control including building management system. 1.4 Ordering Information • V850ES/JH3-E Part Number μ 128-pin plastic LQFP (fine pitch) (14 × 20) PD70F3778GF-GAT-AX μ 128-pin plastic LQFP (fine ...
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Pin Configuration (Top View) • V850ES/JH3-E 128-pin plastic LQFP (fine pitch) (14 × 20) μ PD70F3778GF-GAT-AX μ PD70F3781GF-GAT-AX AV REF0 AV SS P40/SIF0/TXDC3/SDA01/RTP00 P41/SOF0/RXDC3/SCL01/RTP01 P42/SCKF0/TIAA40/TOAA40/RTP02 P43/SIE0/TXDC4/RTP03/HLDAK P44/SOE0/RXDC4/RTP04/HLDRQ P45/SCKE0/TIAA41/TOAA41/RTP05 UDMF UDPF UV DD Note 1 FLMD0 V DD Note 2 ...
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V850ES/JJ3-E 144-pin plastic LQFP (fine pitch) (20 × 20) μ PD70F3784GJ-GAE- REF0 P40/SIF0/TXDC3/SDA01/RTP00 3 P41/SOF0/RXDC3/SCL01RTP01 4 P42/SCKF0/TIAA40/TOAA40/RTP02 5 P43/SIE0/TXDC4/RTP03 6 P44/SOE0/RXDC4/RTP04 7 P45/SCKE0/TIAA41/TOAA41/RTP05 8 UDMF 9 UDPF Note 1 FLMD0 ...
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Pin names A0 to A23: Address bus AD0 to AD15: Address/data bus ADTRG: A/D trigger input ANI0 to ANI11: Analog input ASCKC0: Asynchronous serial clock ASTB: Address strobe AV : Analog reference voltage REF0 AV : Grand for analog pin ...
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Function Block Configuration 1.6.1 Internal block diagram • V850ES/JH3-E Timer/counter function TIAB00 to TIAB02, TIAB10 to TIAB13, EVTAB1, 16-bit timer/ TRGAB1, event TOAB1OFF counter AB: TOAB00 to TOAB02 TOAB10 to TOAB13 TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 ...
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V850ES/JJ3-E Timer/counter function TIAB00 to TIAB03, TIAB10 to TIAB13, EVTAB1, 16-bit timer/ TRGAB1, event TOAB1OFF counter AB: TOAB00 to TOAB03 TOAB10 to TOAB13 TOAB1T1 to TOAB1T3, TOAB1B1 to TOAB1B3 TIAA00 to TIAA50, 16-bit timer/ TIAA01 to TIAA51, ...
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Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × ...
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Real-time counter (for watch) The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. ...
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CRC function A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on-chip. (17) DCU (debug control unit) An on-chip debug function that uses the JTAG (Joint Test Action ...
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List of Pin Functions The names and functions of the pins of the V850ES/JH3-E and V850ES/JJ3-E are described below. There are three types of pin I/O buffer power supplies: AV power supplies and the pins is described below. Power ...
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Port pins Pin Name I/O Function P02 I/O Port 0 2-bit I/O port P03 Input/output can be specified in 1-bit units. Port 2 P20 I/O 7-bit I/O port (V850ES/JH3-E) P21 8-bit I/O port (V850ES/JJ3-E) P22 Input/output can be specified ...
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Pin Name I/O Function P50 I/O Port 5 5-bit I/O port (V850ES/JH3-E) P51 10-bit I/O port (V850ES/JJ3-E) P52 Input/output can be specified in 1-bit units. P53 P54 P55 P56 P57 P58 P59 P70 I/O Port 7 10-bit I/O port (V850ES/JH3-E) ...
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Pin Name I/O Function PCM0 I/O Port CM 2-bit I/O port (V850ES/JH3-E) PCM1 4-bit I/O port (V850ES/JJ3-E) PCM2 Input/output can be specified in 1-bit units. PCM3 PCS0 I/O Port CS 2-bit I/O port (V850ES/JH3-E) PCS2 3-bit I/O port (V850ES/JJ3-E) PCS3 ...
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Non-port Pins Pin Name I/O A0 Output Address bus for external memory (when using separate bus A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 ...
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Pin Name I/O AD0 I/O Address/data bus for external memory AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ADTRG Input External trigger input for A/D converter ANI0 Input Analog voltage input for A/D ...
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Pin Name I/O DCK Input Clock input for on-chip debug DDI Input Data input for on-chip debug DDO Output Data output for on-chip debugging, In the on-chip debug mode, high-level output is forcibly set. DMS Input Mode select signal input ...
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Pin Name I/O INTP20 Input External interrupt request input (maskable, analog noise elimination) INTP21 INTP22 INTP23 INTP24 INTP25 KR0 Input Key interrupt input (on-chip analog noise eliminator) KR1 KR2 KR3 KR4 KR5 KR6 KR7 NMI Input External interrupt input (non-maskable, ...
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Pin Name I/O RD Output Read strobe signal output for external memory − REGC Connection of regulator output stabilization capacitance (4.7 RESET Input System reset input RTC1HZ Output Real-time counter correction clock (1 Hz) output RTCCL Output Real-time counter clock ...
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Pin Name I/O SCL00 I/O Serial clock I/O (I N-ch open-drain output selectable SCL01 SCL02 SCL03 SCL04 SDA00 I/O Serial transmit/receive data I/O (I N-ch open-drain output selectable SDA01 SDA02 SDA03 SDA04 SIE0 Input Serial receive data input (CSIE0, CSIE1) ...
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Pin Name I/O TIAA00 Input External event count input/capture trigger input/external trigger input (TAA0) TIAA01 Capture trigger input (TAA0) TIAA10 External event count input/capture trigger input/external trigger input (TAA1) TIAA11 Capture trigger input (TAA1) TIAA20 External event count input/capture trigger ...
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Pin Name I/O TOAA20 Output Timer output (TAA2) N-ch open-drain output selectable TOAA21 TOAA30 Timer output (TAA3) N-ch open-drain output selectable TOAA31 TOAA40 Timer output (TAA4) N-ch open-drain output selectable TOAA41 TOAA50 Timer output (TAA5) N-ch open-drain output selectable TOAA51 ...
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Pin Name I/O TXDC0 Output Serial transmit data output (UARTC0 to UARTC7) N-ch open-drain output selectable TXDC1 TXDC2 TXDC3 TXDC4 TXDC5 TXDC6 TXDC7 EXCLK Input External USB clock signal input UDMAAK0 Output DMA acknowledge for USB UDMAAK1 UDMARQ0 Input DMA ...
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Pin States The operation states of pins in the various operation modes are described below. Table 2-2. Pin Operation Status in Each Operation Mode Pin Name When Power Is During Reset Note 1 Turned On (Other than When Power ...
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Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (1/4) Pin Name Alternate Function P02 NMI P03 INTP00/ADTRG/EXCLK P20 TIAB02/TOAB02/INTP01 P21 TIAB00/TOAB00/RTCDIV/RTCCL P22 TIAB01/TOAB01/RTC1HZ/INTP02 ...
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Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (2/4) Pin Name Alternate Function P50 INTP07/DDI P51 INTP08/DDO P52 INTP09/DCK P53 INTP10/DMS P54 INTP11/DRST P55 SDA04/INTP23/UDMARQ1 P56 SCL04/INTP24/UDMAAK1 P57 SIF6/TXDC7 P58 SOF6/RXDC7 P59 SCKF6/INTP25 P70 to P79 ANI0 ...
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Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (3/4) Pin Name Alternate Function PCS0 CS0 PCS2 CS2 PCS3 CS3 PCT0 WR0 PCT1 WR1 PCT4 RD PCT6 ASTB PDH0 A16/SIE1 PDH1 A17/SOE1 PDH2 A18/SCKE1 PDH3 A19/SIF4/TXDB0 PDH4 A20/SOF4/RXDB0 ...
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Table 2-3. Pin I/O Circuit Types and Connection of Unused Pins (4/4) Pin Name Alternate Function − P1MDC − P1TXD0 − P1TXD1 − P1TXD2 − P1TXD3 − P1TXEN − P1TXER − REGC − RESET − UDMF − UDPF − UV ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable V SS Input enable Type 10-D Data Open drain Output disable Note Input enable Type 10-N Data Open drain Output disable Note Input ...
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Cautions When the power is turned on, the following pins may output an undefined level temporarily even during reset. • P51/INTP08/DDO pin CHAPTER 2 PIN FUNCTIONS User’s Manual U19601EJ2V0UD 57 ...
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The CPU of the V850ES/JH3-E and V850ES/JJ3-E is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time (operating with main clock (f Memory space ...
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CPU Register Set The registers of the V850ES/JH3-E and V850ES/JJ3-E can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. ...
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Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. Any of these registers can be used to store a data variable ...
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System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. ...
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Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to ...
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NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those ...
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Program status word (PSW) The program status word (PSW collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this ...
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Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a ...
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Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the ...
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Operation Modes The V850ES/JH3-E and V850ES/JJ3-E have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches ...
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Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...
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Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a ...
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Memory map The areas shown below are reserved in the V850ES/JH3-E and V850ES/JJ3-E. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH (80 KB) 03FEC000H 03FEBFFFH Use prohibited 01000000H 00FFFFFFH External memory area (8 MB) 00800000H 007FFFFFH External memory area ...
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CHAPTER 3 CPU FUNCTION Figure 3-3. Memory Map of CS1 Access-prohibited area Bridge-rerated ...
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Note Use of this area is allowed only when using the V850ES/JJ3-E. When using the V850ES/JH3-E, this area cannot be used. 72 CHAPTER 3 CPU FUNCTION Figure 3-4. Program Memory Map ...
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Areas (1) Internal ROM area reserved as an internal ROM area. (a) Internal ROM (256 KB) μ In the PD70F3778, 256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products. Accessing ...
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Internal ROM (512 KB) 512 KB are allocated to addresses 00000000H to 0007FFFFH in the following products. Accessing addresses 00080000H to 000FFFFFH is prohibited. • μ PD70F3780, 70F3782, 70F3783, 70F3784, 70F3785, 70F3786 (2) Internal RAM area ...
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CHAPTER 3 CPU FUNCTION (a) Internal RAM (60 KB) An internal RAM area allocated to addresses 03FF0000H to 03FFEFFFH in the V850ES/JH3- E and V850ES/JJ3-E. Figure 3-8. Internal RAM Area (60 KB) Physical address space 0 ...
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Data-only RAM (64 KB) A data-only RAM allocated to addresses 00280000H to 0028FFFFH in the following products. μ • PD70F3781, 70F3782, 70F3783, 70F3785, 70F3786 Figure 3-10. Data-Only RAM Area (64 KB) 76 CHAPTER 3 CPU ...
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On-chip peripheral I/O area addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-11. On-Chip Peripheral I/O Area Physical address space ...
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Recommended use of address space The architecture of the V850ES/JH3-E and V850ES/JJ3-E requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in ...
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CHAPTER 3 CPU FUNCTION (a) Application example of wraparound (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including ...
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Figure 3-12. Recommended Memory Map Program space ...
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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H Note 2 FFFFF006H Port DH register FFFFF008H Port CS register FFFFF00AH Port CT register FFFFF00CH Port CM register ...
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Address Function Register Name FFFFF098H DMA source address register 3L FFFFF09AH DMA source address register 3H FFFFF09CH DMA destination address register 3L FFFFF09EH DMA destination address register 3H FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 ...
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Address Function Register Name FFFFF114H Interrupt control register FFFFF116H Interrupt control register FFFFF118H Interrupt control register FFFFF11AH Interrupt control register FFFFF11CH Interrupt control register FFFFF11EH Interrupt control register FFFFF120H Interrupt control register FFFFF122H Interrupt control register FFFFF124H Interrupt control register ...
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Address Function Register Name FFFFF164H Interrupt control register FFFFF166H Interrupt control register FFFFF168H Interrupt control register FFFFF16AH Interrupt control register FFFFF16CH Interrupt control register FFFFF16EH Interrupt control register FFFFF170H Interrupt control register FFFFF172H Interrupt control register FFFFF174H Interrupt control register ...
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Address Function Register Name FFFFF1A8H Interrupt control register FFFFF1AAH Interrupt control register FFFFF1ACH Interrupt control register FFFFF1AEH Interrupt control register FFFFF1B0H Interrupt control register FFFFF1B2H Interrupt control register FFFFF1B4H Interrupt control register FFFFF1B6H Interrupt control register FFFFF1B8H Interrupt control register ...
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Address Function Register Name FFFFF210H A/D conversion result register 0 FFFFF211H A/D conversion result register 0H FFFFF212H A/D conversion result register 1 FFFFF213H A/D conversion result register 1H FFFFF214H A/D conversion result register 2 FFFFF215H A/D conversion result register 2H ...
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Address Function Register Name FFFFF408H Port 4 register FFFFF408H Port 4 register L FFFFF409H Port 4 register H FFFFF40AH Port 5 register FFFFF40AH Port 5 register L FFFFF40BH Port 5 register H FFFFF40EH Port 7 register FFFFF40EH Port 7 register ...
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Address Function Register Name FFFFF468H Port 4 function control register FFFFF468H Port 4 function control register L FFFFF469H Port 4 function control register H FFFFF46AH Port 5 function control register FFFFF46AH Port 5 function control register L FFFFF46BH Port 5 ...
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Address Function Register Name FFFFF591H High impedance output control register 1 FFFFF5A0H TAA0 noise elimination control register FFFFF5A2H TAA1 noise elimination control register FFFFF5A4H TAA2 noise elimination control register FFFFF5A6H TAA3 noise elimination control register FFFFF5A8H TAA4 noise elimination control ...
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Address Function Register Name FFFFF64AH TAA1 counter read buffer register FFFFF64CH TAA1 I/O control register 4 FFFFF650H TAA2 control register 0 FFFFF651H TAA2 control register 1 FFFFF652H TAA2 I/O control register 0 FFFFF653H TAA2 I/O control register 1 FFFFF654H TAA2 ...
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Address Function Register Name FFFFF68AH TAA5 counter read buffer register FFFFF68CH TAA5 I/O control register 4 FFFFF6C0H Oscillation stabilization time select register FFFFF6C1H PLL lockup time specification register FFFFF6D0H Watchdog timer mode register 2 FFFFF6D1H Watchdog timer enable register FFFFF6E0H ...
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Address Function Register Name FFFFFA03H UARTC0 option control register 0 FFFFFA04H UARTC0 status register FFFFFA06H UARTC0 receive data register FFFFFA06H UARTC0 receive data register L FFFFFA08H UARTC0 transmit data register FFFFFA08H UARTC0 transmit data register L FFFFFA0AH UARTC0 option control ...
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Address Function Register Name FFFFFA44H UARTC4 status register FFFFFA46H UARTC4 receive data register FFFFFA46H UARTC4 receive data register L FFFFFA48H UARTC4 transmit data register FFFFFA48H UARTC4 transmit data register L FFFFFA4AH UARTC4 option control register 1 FFFFFA50H UARTC5 control register ...
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Address Function Register Name FFFFFAA4H TMM2 compare register 0 FFFFFAB0H TMM3 control register 0 FFFFFAB4H TMM3 compare register 0 FFFFFAD0H Sub-count register FFFFFAD2H Second count register FFFFFAD3H Minute count register FFFFFAD4H Hour count register FFFFFAD5H Week count register FFFFFAD6H Day ...
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Address Function Register Name FFFFFB80H UARTB0 control register 0 FFFFFB82H UARTB0 control register 2 FFFFFB84H UARTB0 status register FFFFFB86H UARTB0 receive data register AP FFFFFB86H UARTB0 receive data register FFFFFB88H UARTB0 transmit data register FFFFFB8AH UARTB0 FIFO control register 0 ...
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Address Function Register Name FFFFFC12H External interrupt falling edge specification register 9 FFFFFC12H External interrupt falling edge specification register 9H INTF9H FFFFFC13H External interrupt falling edge specification register 9L INTF9L FFFFFC20H External interrupt rising edge specification register 0 FFFFFC24H External ...
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Address Function Register Name FFFFFD20H CSIF2 control register 0 FFFFFD21H CSIF2 control register 1 FFFFFD22H CSIF2 control register 2 FFFFFD23H CSIF2 status register FFFFFD24H CSIF2 receive data register FFFFFD24H CSIF2 receive data register L FFFFFD26H CSIF2 transmit data register FFFFFD26H ...
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Address Function Register Name FFFFFD80H IIC shift register 0 FFFFFD82H IIC control register 0 FFFFFD83H Slave address register 0 FFFFFD84H IIC clock select register 0 FFFFFD85H IIC function expansion register 0 FFFFFD86H IIC status register 0 FFFFFD8AH IIC flag register ...
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Programmable peripheral I/O registers The BPC register is used to select the programmable peripheral I/O register area. The BPC register is valid only in the (1) Peripheral I/O area select control register (BPC) This register can be read or ...
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Special registers Special registers are registers that are protected from being written with illegal data due to a program loop. The V850ES/JH3-E and V850ES/JJ3-E have the following eight special registers. • Power save control register (PSC) • Clock control ...
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Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in ...
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Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first ...
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System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After ...
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Cautions (1) Registers to be set first Be sure to set the following registers first when using the V850ES/JH3-E and V850ES/JJ3-E. • System wait control register (VSWC) • On-chip debug mode register (OCDM) • Watchdog timer mode register 2 ...
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Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus ...
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Peripheral Function Register Name CSIE ( CEnCTL0 CEnTX0 (CEnTX0H, CEnTX0L) CenCS (CEnCSL) CEnSTR UARTB ( UBnTX UBnRX UBnRXAP UBnFIS0 UBnFIS1 C00 to I C04 IICS0 to IICS4 CRC CRCD CAN controller ...
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CHAPTER 3 CPU FUNCTION Number of clocks necessary for access = × k Note Digits below the decimal point are rounded up. Caution Accessing the above registers is prohibited in the ...
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Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...
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Features I/O ports • V850ES/JH3- tolerant/N-ch open-drain output selectable: 48 • V850ES/JJ3-E: 100 5 V tolerant/N-ch open-drain output selectable: 59 Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/JH3-E features a total of 84 ...
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Figure 4-1. Port Configuration Diagram (V850ES/JH3-E) Port 0 Port 2 Port 3 Port 4 Port 5 Port 7 Figure 4-2. Port Configuration Diagram (V850ES/JJ3-E) Port 0 Port 2 Port 3 Port 4 Port 5 Port 7 Port 9 110 CHAPTER ...
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Port Configuration Table 4-3. Port Configuration (V850ES/JH3-E) Item Control register Port n mode register (PMn CM, CS, CT, DH, DL) Port n mode control register (PMCn ...
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Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the ...
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Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be ...
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Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, ...
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Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in ...
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Port setting Set a port as illustrated below. Figure 4-3. Setting of Each Register and Pin Function Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function ...
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Port 0 Port 0 is 2-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Pin Name Pin No. Alternate-Function Pin Name V850ES/ V850ES/ JH3-E JJ3-E P02 21 21 NMI ...
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Port 0 mode control register (PMC0) After reset: 00H R/W 7 PMC0 0 PMC03 0 I/O port 1 INTP00 input/ADTRG input/EXCLK input PMC02 0 I/O port 1 NMI input (4) Port 0 function control register (PFC0) After reset: 00H ...
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Port 0 function register (PF0) After reset: 00H R PF0 0 0 PF0n 0 Normal output 1 N-ch open-drain output CHAPTER 4 PORT FUNCTIONS Address: FFFFFC60H PF03 PF02 Control of normal ...
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Port 2 Port 7-bit (V850ES/JH3-E)/8-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port 2 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E P20 38 38 TIAB02/TOAB02/INTP01 ...
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Port 2 mode register (PM2) (a) V850ES/JH3-E After reset: FFH R PM2 1 PM26 PM2n 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFH R PM2 PM27 PM26 PM2n 0 Output mode 1 ...
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Port 2 mode control register (PMC2) (a) V850ES/JH3-E After reset: 00H R/W 7 PMC2 0 PMC26 PMC26 0 I/O port 1 TIAA31 input/TOAA31 output/INTP05 input/UDMAAK0 output PMC25 0 I/O port 1 SCKF1 I/O/TIAA30 input/TOAA30 output/UDMARQ0 input PMC24 0 I/O ...
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CHAPTER 4 PORT FUNCTIONS (b) V850ES/JJ3-E After reset: 00H R/W Address: FFFFF444H 7 6 PMC2 PMC27 PMC26 PMC27 0 I/O port 1 TIAB03 input/TOAB03 output/INTP21 input PMC26 0 I/O port 1 TIAA31 input/TOAA31 output/INTP05 input/UDMAAK0 output PMC25 0 I/O port ...
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Port 2 function control register (PFC2) (a) V850ES/JH3-E After reset: 00H R/W 7 PFC2 0 PFC26 (b) V850ES/JJ3-E After reset: 00H R/W 7 PFC2 PFC27 PFC26 Remark For details of alternate function specification, see 4.3.2 (6) Port 2 alternate ...
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Port 2 alternate function specifications PFCE27 PFC27 PFCE26 PFC26 PFCE25 PFC25 PFCE24 PFC24 0 0 ...
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PFCE20 PFC20 (7) Port 2 function register (PF2) (a) V850ES/JH3-E After reset: 00H R/W 7 PF2 0 PF26 PF2n 0 Normal output 1 N-ch open-drain output (b) V850ES/JJ3-E After reset: 00H R/W ...
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Port 3 Port 8-bit port that controls I/O in 1-bit units. Port 3 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E P30 28 28 TXDC0/SIF2/TIAA00/TOAA00 P31 29 29 RXDC0/SOF2/TIAA01/TOAA01 P32 30 ...
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Port 3 mode control register (PMC3) After reset: 00H R/W PMC3 PMC37 PMC36 PMC37 0 I/O port 1 RXDC2 input/SCL02 I/O/CRXD0 input PMC36 0 I/O port 1 TXDC2 output/SDA02 I/O/CTXD0 output PMC35 0 I/O port 1 SCKF4 I/O/TIAA21 input/TOAA21 ...
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Port 3 function control register (PFC3) After reset: 00H R/W PFC37 PFC36 PFC3 Remark For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. (5) Port 3 function control expansion register (PFCE3) After reset: 00H ...
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PFCE35 PFC35 Notes 1. The SCKF4 function is assigned to the PDH5 pin as well as the P35 pin. When using the P35 pin for the SCKF4 function, do not specify the ...
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Port 3 function register (PF3) After reset: 00H R/W PF3 PF37 PF36 PF3n Control of normal output or N-ch open-drain output ( Normal output (CMOS output) 1 N-ch open-drain output CHAPTER 4 PORT FUNCTIONS ...
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Port 4 Port 6-bit (V850ES/JH3-E) and 9-bit (V850ES/JJ3-E) port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E P40 3 3 SIF0/TXDC3/SDA01/RTP00 P41 4 ...
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Port 4 register (P4) (a) V850ES/JH3-E After reset: 00H (output latch P4n 0 Outputs 0. 1 Outputs 1. (b) V850ES/JJ3-E After reset: 0000H (output latch (P4H (P4L) P47 P46 P4n 0 ...
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Port 4 mode register (PM4) (a) V850ES/JH3-E After reset: FFH R/W PM4 1 PM4n 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFFFH 15 PM4 (PM4H) 1 (PM4L) PM47 PM4n 0 1 134 CHAPTER 4 PORT FUNCTIONS ...
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Port 4 mode control register (PMC4) (a) V850ES/JH3-E After reset: 00H R/W PMC4 0 0 PMC45 0 I/O port 1 SCKE0 I/O/TIAA41 input/TOAA41 output/RTP05 output PMC44 0 I/O port 1 SOE0 output/RXDC4 input/RTP04 output/HLDRQ input PMC43 0 I/O port ...
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V850ES/JJ3-E After reset: 0000H (output latch) 15 PMC4 (PMC4H) 0 (PMC4L) PMC47 PMC46 PMC48 0 I/O port 1 SCKF5 I/O/INTP22 input PMC47 0 I/O port 1 SOF5 output/RXDC6 input/RTP07 output PMC46 0 I/O port 1 SIF5 input/TXDC6 output/RTP06 output ...
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Port 4 function control register (PFC4) (a) V850ES/JH3-E After reset: 00H R/W PFC4 0 0 (b) V850ES/JJ3-E After reset: 0000H 15 PFC4 (PFC4H) 0 (PFC4L) PFC47 PFC46 Remarks 1. For details of alternate-function specification, see 4.3.4 (6) function specifications. ...
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Port 4 alternate function specifications Note PFC48 0 1 Note V850ES/JJ3-E only Note Note PFCE47 PFC47 Note V850ES/JJ3-E only Note Note PFCE46 PFC46 ...
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CHAPTER 4 PORT FUNCTIONS PFCE42 PFC42 0 0 SCKF0 I TIAA40 input 1 0 TOAA40 output 1 1 RTP02 output PFCE41 PFC41 0 0 SOF0 output 0 1 RXDC3 input 1 0 SCL01 I RTP01 output ...
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Port 4 function register (PF4) (a) V850ES/JH3-E After reset: 00H R/W PF4 0 PF4n 0 Normal output (CMOS output) 1 N-ch open-drain output (b) V850ES/JJ3-E After reset: 0000H 15 PF4 (PF4H) 0 (PF4L) PF47 PF4n 0 Normal output (CMOS ...
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Port 5 Port 5-bit (V850ES/JH3-E)/10-bit (V850ES/JJ3-E) port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-10. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name V850ES/ V850ES/ JH3-E ...
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Port 5 register (P5) (a) V850ES/JH3-E After reset: 00H (output latch P5n 0 Outputs 0. 1 Outputs 1. (b) V850ES/JJ3-E After reset: 0000H (output latch (P5H) 0 (P5L) P57 P5n 0 Outputs 0. 1 Outputs ...
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Port 5 mode register (PM5) (a) V850ES/JH3-E After reset: FFH R/W PM5 1 1 PM5n 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFFFH 15 PM5 (PM5H) 1 (PM5L) PM57 PM56 PM5n 0 Output mode 1 Input ...
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Port 5 mode control register (PMC5) (a) V850ES/JH3-E After reset: 00H R/W PMC5 0 PMC54 0 I/O port 1 INTP11 input PMC53 0 I/O port 1 INTP10 input PMC52 0 I/O port 1 INTP09 input PMC51 0 I/O port ...
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CHAPTER 4 PORT FUNCTIONS (b) V850ES/JJ3-E After reset: 0000H R PMC5 (PMC5H (PMC5L) PMC57 PMC56 PMC59 0 I/O port 1 SCKF6 I/O/INTP25 input PMC58 0 I/O port 1 SOF6 output/RXDC7 input PMC57 0 I/O port 1 ...
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Port 5 function control register (PFC5) (V850ES/JJ3-E only) After reset: 0000H 15 PFC5 (PFC5H) 0 (PFC5L) PFC57 Remarks 1. For details of alternate function specification, see 4.3.5 (6) function specifications. 2. The PFC5 register can be read or written ...
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PFCE56 PFC56 PFCE55 PFC55 (7) Port 5 function register (PF5) (a) V850ES/JH3-E After reset: 00H R/W PF5 0 0 PF5n Control of normal output ...
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Port 7 Port 10-bit (V850ES/JH3-E) and 12-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-11. Port 7 Alternate-Function Pins Pin Name Pin No. ...
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Port 7 register H, port 7 register L (P7H, P7L) (a) V850ES/JH3-E After reset: 00H (output latch P7H P77 P76 P7L P7n 0 Outputs 0. 1 Outputs 1. (b) V850ES/JJ3-E After reset: 00H (output latch) P7H 0 ...
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Port 7 mode register H, port 7 mode register L (PM7H, PM7L) (a) V850ES/JH3-E After reset: FFH R/W PM7H 1 PM7L PM77 PM76 PM7n 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFH R/W PM7H 1 PM7L ...
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Port 9 Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-12. Port 9 Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E ...
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Port 9 register (P9) After reset: 0000H (output latch (P9H) P915 (P9L) P97 P9n 0 Outputs 0. 1 Outputs 1. Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the ...
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Port 9 mode control register (PMC9) After reset: 0000H 15 PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 (PMC9L) PMC97 PMC96 PMC915 0 I/O port 1 SCKF3 I/O/TIAA51 input/TOAA51 output/A15 output PMC914 0 I/O port 1 SOF3 output/RXDB1 input/INTP20 ...
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PMC97 0 I/O port 1 TENC00 input/TIT01 input/KR7 input/TOT01 output/A7 output PMC96 0 I/O port 1 TECR0 input/TIT00 input/KR06 input/TOT00 output/A6 output PMC95 0 I/O port 1 TOAB1B3 output/EVTAB1 input/KR5 input/INTP16 input/A5 output PMC94 0 I/O port 1 TOAB1T3 output/TOAB13 ...
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Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 register to FEFFH and the PFCE9 registers ...
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Port 9 alternate function specifications PFCE915 PFC915 PFCE914 PFC914 PFCE913 PFC913 PFC912 0 1 Caution ...
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CHAPTER 4 PORT FUNCTIONS PFCE99 PFC99 0 0 SIE1 input 0 1 TXDC5 output 1 0 SDA03 I output Caution The SIE1 function is assigned to the PDH0 pin as well as the P99 pin. When using ...
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PFCE94 PFC94 Caution KR4 and TIAB13 are alternate functions. When using the pin for the TIAB13 function, disable key return detection of KR4, which is the alternate function (set the KRM.KRM4 bit ...
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Port 9 function register (PF9) After reset: 0000H R PF9 PF915 PF914 (PF9L) PF97 PF96 PF9n Control of normal output or N-ch open-drain output ( 15) 0 Normal output (CMOS output) 1 N-ch open-drain ...
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Port CM Port 2-bit (V850ES/JH3-E)/4-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-13. Port CM Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ ...
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Port CM mode register (PMCM) (a) V850ES/JH3-E After reset: FFH R/W PMCM 1 1 PMCMn 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFH R/W PMCM 1 1 PMCMn 0 Output mode 1 Input mode CHAPTER 4 ...
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Port CM mode control register (PMCCM) (a) V850ES/JH3-E After reset: 00H R/W PMCCM 0 PMCCM1 0 I/O port 1 CLKOUT output PMCCM0 0 I/O port 1 WAIT input (b) V850ES/JJ3-E After reset: 00H R/W PMCCM 0 PMCCM3 0 I/O ...
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Port CS Port 2-bit (V850ES/JH3-E)/3-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-14. Port CM Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ ...
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Port CS mode register (PMCS) (a) V850ES/JH3-E After reset: FFH R/W PMCS 1 PMCSn 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFH R/W PMCS 1 PMCSn 0 Output mode 1 Input mode 164 CHAPTER 4 PORT ...
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Port CS mode control register (PMCCS) (a) V850ES/JH3-E After reset: 00H R/W PMCCS 0 0 PMCCS2 0 I/O port 1 CS2 output PMCCS0 0 I/O port 1 CS0 output (b) V850ES/JJ3-E After reset: 00H R/W PMCCS 0 0 PMCCS3 ...
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Port CT Port 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-15. Port CT Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E ...
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Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O port 1 ...
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Port DH Port 6-bit (V850ES/JH3-E)/8-bit (V850ES/JJ3-E) port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-16. Port DH Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ ...
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Port DH register (PDH) (a) V850ES/JH3-E After reset: 00H (output latch) PDH 0 0 PDHn 0 Outputs 0. 1 Outputs 1. (b) V850ES/JJ3-E After reset: 00H (output latch) PDH PDH7 PDH6 PDHn 0 Outputs 0. 1 Outputs 1. CHAPTER ...
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Port DH mode register (PMDH) (a) V850ES/JH3-E After reset: FFH R/W PMDH 1 PMDHn 0 Output mode 1 Input mode (b) V850ES/JJ3-E After reset: FFH R/W PMDH PMDH7 PMDH6 PMDHn 0 Output mode 1 Input mode 170 CHAPTER 4 ...
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Port DH mode control register (PMCDH) (a) V850ES/JH3-E After reset: 00H R/W PMCDH 0 0 PMCDH5 0 I/O port 1 A21 output/SCKF4 I/O PMCDH4 0 I/O port 1 A20 output/SOF4 output/RXDB0 input PMCDH3 0 I/O port 1 A19 output/SIF4 ...
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V850ES/JJ3-E After reset: 00H R/W PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDH7 0 I/O port 1 A23 output PMCDH6 0 I/O port 1 A22 output PMCDH5 0 I/O port 1 A21 output/SCKF4 I/O PMCDH4 0 I/O ...
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Port DH function control register (PFCDH) After reset: 00H R PFCDH 0 0 Remark For details of alternate-function specification, see 4.3.11 (6) Port DH alternate function specifications. (5) Port DH function control expansion register (PFCEDH) After reset: ...
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PFCDH2 0 A18 output 1 SCKE1 I/O Caution The SCKE1 function is assigned to the PDH2 pin as well as the P911 pin. When using the PDH2 pin for the SCKE1 function, do not set the P911 pin to be ...
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Port DL Port 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-17. Port DL Alternate-Function Pins Pin Name Pin No. V850ES/ V850ES/ JH3-E JJ3-E ...
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Port DL register (PDL) After reset: 0000H (output latch) 15 PDL (PDLH) PDL15 (PDLL) PDL7 PDLn 0 Outputs 0. 1 Outputs 1. Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the ...
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Port DL mode control register (PMCDL) After reset: 0000H 15 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 (PMCDLL) PMCDLn 0 1 Remarks 1. The PMCDL register can be read or ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P02 NMI Input P02 = Setting not required P03 INTP00 Input P03 = Setting not required ADTRG Input P03 = Setting not required EXCLK Input P03 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P25 SCKF1 I/O P25 = Setting not required TIAB30 Input P25 = Setting not required TOAB30 Output P25 = Setting not required UDMARQ0 Input P25 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Note 1 P33 SIF4 Input P33 = Setting not required TXDB0 Output P33 = Setting not required TIAA11 Input P33 = Setting not required TOAA11 Output P33 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P40 SIF0 Input P40 = Setting not required TXDC3 Output P40 = Setting not required SDA01 I/O P40 = Setting not required RTP00 Output P40 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note P46 SIF5 Input P46 = Setting not required TXDC6 Output P46 = Setting not required RTP06 Output P46 = Setting not required Note P47 SOF5 Output P47 = ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O Note P56 SCL04 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 INTP24 Input P55 = Setting not required PM55 = Setting not required ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P90 TOAB1T1 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 TOAB11 Output P90 = Setting not required PM90 = Setting not required PMC90 ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P93 TOAB1B2 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 Note 1 TRGAB1 Input P93 = Setting not required PM93 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P96 TECR0 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 Note 1 TIT00 Input P96 = Setting not required PM96 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P910 SOE1 Output P910 = Setting not required RXDC5 Output P910 = Setting not required SCL03 I/O P910 = Setting not required Note 1 A10 Output P910 = Setting ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O P915 SCKF3 I/O P915 = Setting not required PM915 = Setting not required TIAA50 Input P915 = Setting not required PM915 = Setting not required TOAA0 Output P915 = ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDH3 A19 Output PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1 Note 1 SIF4 Input PDH3 = Setting not required PMDH3 = Setting not ...
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Pin Name Alternate Function Pnx Bit of Pn Register Name I/O PDL5 AD5 I/O PDL5 = Setting not required PMDL5 = Setting not required Note FLMD1 Input PDL5 = Setting not required PMDL5 = Setting not required PDL6 AD6 I/O ...
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Cautions 4.5.1 Cautions on setting port pins (1) In the V850ES/JH3-E and V850ES/JJ3-E, the general-purpose port functions share pins with several peripheral function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function ...
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The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin is shown below. Setting Procedure <1> <2> <3> <4> <2> communication may be affected since the alternate-function SOF0 output ...
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Figure 4-4. Example of Switching from P02 to NMI (Incorrect) PMC0 PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence detector Remark [Example 2] Switching from external pin (NMI) to ...
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Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is ...
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Cautions on on-chip debug pins (V850ES/JH3-E only) The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P54/INTP11/DRST pin is initialized to function as an on-chip debug pin (DRST). If ...
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CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JH3-E and V850ES/JJ3-E are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from multiplexed bus output ...
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Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 Note 1 A16 to ...
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Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-3. Pin Statuses When Internal ...