UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 384

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
382
(e) TABn counter read buffer register (TABnCNT)
(f) TABn capture/compare register 0 (TABnCCR0)
(g) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
The count value of the 16-bit counter can be read by reading the TABnCNT register.
If D
signal (INTTABnCC0) is generated when the number of external event counts reaches (D
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
However, the set value of the TABnCCR1 to TABnCCR3 registers are transferred to the CCR1 to CCR3
buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3
buffer registers, compare match interrupt request signals (INTTABnCC1 to INTTABnCC3) are
generated.
Therefore, mask the interrupt signals by using the interrupt mask flags (TABnCCMK1 to TABnCCMK3).
Caution For TAB0, when an external clock is used as the count clock, the external clock can be
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
0
Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
is set to the TABnCCR0 register, the counter is cleared and a compare match interrupt request
input only from the TIAB00 pin.
TAB0IOC1.TAB0IS0 bits to 00 (capture trigger input (TIAB00 pin): no edge detection).
2. n = 0, 1
used in the external event count mode.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
User’s Manual U19601EJ2V0UD
At this time, set the TAB0IOC1.TAB0IS1 and
0
+ 1).

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