UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1120

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.9.2 Reading reception data
procedures shown in Figures 21-49 and 21-50.
processing to store data in the message buffer and at the end of this storing processing.
processing, the C0MCTRLm.MUC bit of the message buffer is set (1) (refer to Figure 21-29).
the CPU is prohibited from rewriting the C0MCTRLm.RDY bit of the message buffer in which the data is to be stored.
Completion of this data storing processing may be delayed by a CPU’s access to any message buffer.
1118
CAN standard
ID format
If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended
While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the
Before the data is completely stored, the receive history list is written. During this data storing period (MUC bit = 1),
Remark m = 0 to 31
C0INTS.CINTS1
bit
INTC0REC
signal
Operation of CAN controller
MUC bit
DN bit
(1)
(11)
ID
Figure 21-29. DN and MUC Bit Setting Period (in Standard ID Format)
(1)
(1)
(1)
DLC
(4)
DATA0-DATA7
CHAPTER 21 CAN CONTROLLER
(0-64)
User’s Manual U19601EJ2V0UD
CRC
(16)
ACK EOF
(2)
(7)
The DN and MUC bits are
set (1) at the same time.
DATA, DLC, ID → Message buffer
Message stored
IFS
The DN bit is set (1) and the
MUC bit is cleared (0) at the
same time.
During this storing
Recessive
Dominant