UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1507

no-image

UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
23.6.2 Descriptor mechanism
stores transmit data and receive data is not contiguous. The Ethernet controller uses the following three types of
descriptors.
Configuration of Descriptor Chain (During Packet Reception)).
Descriptor chain).
chain to RXDP or the first address of a transmit descriptor chain to TXDP, and setting the RXS or TXS bit of the
ETHMODE register.
The Ethernet controller supports a descriptor mechanism to support a situation where the memory space that
• Buffer descriptor
• Link pointer
• End of chain
Each descriptor expands data aligned with 2 words (64 bits) on memory (refer to Figure 23-29 Example of
The Ethernet controller can consecutively process two or more descriptors in one DMA transfer (refer to 23.6.2 (6)
Reception DMA transfer or transmission DMA transfer is started by setting the first address of a receive descriptor
A descriptor chain must end with the descriptor of an end of chain.
(1) Format of buffer descriptor
A buffer descriptor is configured of 2 words (64 bits). The lower word consists of control bits. The higher word
indicates the start address value of the data buffer indicated by the descriptor.
T(0) E
31
63
30 29 28 27 26
U
D
S
Figure 23-19. Buffer Descriptor Format
CHAPTER 23 ETHERNET CONTROLLER
O
25
User’s Manual U19601EJ2V0UD
Status
Buffer Address Pointer
16 15
Size
32
0
1505

Related parts for UPD70F3786GJ-GAE-AX