UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1009

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected (n = 0
to 2).
SDA0n
SCL0n
Communication reservations are accepted via the following timing.
Remark
Remark
Hardware processing
1
SDA0n
Program processing
SCL0n
SPDn
STDn
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
2
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
STTn:
STDn:
SPDn:
3
Figure 20-17. Timing for Accepting Communication Reservations
Bit of IICCn register
Bit of IICSn register
Bit of IICSn register
4
Communication
reservation
STTn
=1
Figure 20-16. Communication Reservation Timing
5
6
User’s Manual U19601EJ2V0UD
7
CHAPTER 20 I
Standby mode
8
Generated by master with bus access
9
2
C BUS
Set SPDn
and INTIICn
Write to
IICn
After the IICSn.STDn bit is set to 1, a
Set
STDn
1
2
3
4
5
6
1007

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