UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 906

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

904
(4) CSIFn control register 1 (CFnCTL1)
CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0.
CFnCTL1
After reset: 00H
Notes 1. If n is 0, 4, or 5, set the communication clock (f
Remarks 1. n = 0 to 4 (V850ES/JH3-E)
CFnCKS2
Communication
Communication
Communication
Communication
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
0
2. If n is 1 to 3, or 6, set the communication clock (f
R/W
CFnCKS1
2. When n = 0 or 1, m = 1
CFnCKP
0
0
0
1
1
0
0
1
1
0
0
1
1
n = 0 to 6 (V850ES/JJ3-E)
When n = 2 or 3, m = 2
When n = 4, m = 3
When n = 5 or 6, m = 4
For details of f
Address:
User’s Manual U19601EJ2V0UD
CFnCKS0
CFnDAP
0
1
0
1
0
1
0
1
0
1
0
1
0
CF0CTL1 FFFFFD01H, CF1CTL1 FFFFFD11H,
CF2CTL1 FFFFFD21H, CF3CTL1 FFFFFD31H,
CF4CTL1 FFFFFD41H, CF5CTL1 FFFFFD51H,
CF6CTL1 FFFFFD61H
SOFn
SOFn (output)
SOFn
SOFn (output)
SIFn capture
SIFn capture
SIFn capture
SIFn capture
SCKFn
SCKFn
SCKFn
SCKFn
CFnCKP CFnDAP CFnCKS2 CFnCKS1 CFnCKS0
Communication clock (f
f
f
f
f
f
f
f
External clock (SCKFn)
XX
XX
XX
XX
XX
XX
BRGm
BRGm
(output)
(output)
/4
/6
/8
/12
/16
/32
(I/O)
(I/O)
(I/O)
(I/O)
, see 19.8 Baud Rate Generator.
reception timing in relation to SCKFn
Specification of data transmission/
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
CCLK
D5
D5
D4
D4
)
Note
D4
D4
D3
D3
D3
D3
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
CCLK
D2
D2
CCLK
D2
D2
Mode
) to 8 MHz or lower.
D1
D1
) to 5 MHz or lower.
D1
D1
D0
D0
D0
D0