UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 216

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7.2
5.7.3
entered even if the HLDRQ pin is asserted.
status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold
status is cleared.
214
The bus hold status transition procedure is shown below.
Because the internal system clock is stopped in the STOP, IDLE1, and IDLE2 modes, the bus hold status is not
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
<5> HLDAK = 0
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Bus cycle start request inhibition released
<9> Bus cycle starts
Bus hold procedure
Operation in power save mode
HLDAK (output)
HLDRQ (input)
CHAPTER 5 BUS CONTROL FUNCTION
<1> <2>
User’s Manual U19601EJ2V0UD
<3><4>
<5>
Normal status
Bus hold status
Normal status
<6>
<7><8><9>