UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1096

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1094
(11) CAN0 module interrupt status register (C0INTS)
(a) Read
(b) Write
(a) Read
(b) Write
Note
Caution The status bit of this register is not automatically cleared. Clear it (0) by software if each
CINTS5 to CINTS0
CINTS5 to CINTS0
The C0INTS register indicates the interrupt status of the CAN module.
After reset: 0000H
C0INTS
C0INTS
Interrupt status bit
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
Clear
The CINTS5 bit is set (1) only when the CAN module is woken up from the CAN sleep mode by a
CAN bus operation. The CINTS5 bit is not set (1) when the CAN sleep mode has been released by
software.
0
1
0
1
status must be checked in the interrupt servicing.
Wakeup interrupt from CAN sleep mode
Arbitration loss interrupt
CAN protocol error interrupt
CAN error status interrupt
Interrupt on completion of reception of valid message frame to message buffer m
Interrupt on normal completion of transmission of message frame from message buffer m
CINTS5 to CINTS0 bits are not changed.
CINTS5 to CINTS0 bits are cleared to 0.
No related interrupt source event is generated.
A related interrupt source event is generated.
15
15
0
7
0
0
7
0
R/W
Address: 03FEC058H
14
14
0
6
0
0
6
0
CHAPTER 21 CAN CONTROLLER
User’s Manual U19601EJ2V0UD
CINTS5
CINTS5
Clear
13
13
0
5
0
5
Setting of CINTS5 to CINTS0 bits
Related interrupt source event
CINTS4
CINTS4
CAN interrupt status bit
Clear
12
12
Note
4
4
0
0
CINTS3
CINTS3
Clear
11
11
0
3
0
3
CINTS2
CINTS2
Clear
10
10
0
2
0
2
CINTS1
CINTS1
Clear
9
0
1
9
0
1
CINTS0
CINTS0
Clear
8
0
0
8
0
0