UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1462

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1460
16
7
6
5
4
3
2
1
0
(16) TXSTATUS: Transmission status interrupt register
Bit
This register stores the cumulative result of the transmission status. An INTETMTS interrupt (transmission
status interrupt) is generated if it is not masked by the setting of the TXSTATUS_MASK register. The
INTETMTS interrupt signal is kept asserted while any bit of this register is set.
If an interrupt source masked by a bit of the TXSTATUS_MASK register has been generated, the
corresponding bit of this register is set as well. All the bits of the TXSTATUS register are cleared when the
register is read.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Cautions 1. The transmission status interrupt register is cleared when it is read. It is recommended
TAB
TGNT
LCOL
ECOL
TEDFR
TDFR
TFLOR
TFLER
TCRCE
TGNT
31
23
15
Name
R
R
R
R
0
0
0
7
2. Be sure to set bits 31 to 17 and 15 to 8 to “0”.
to copy interrupt sources to variables so that several interrupt sources that are
generated at the same time can be detected.
This register is read-only, in 32-bit units.
002E 0258H
LCOL
Transmission has been aborted.
A packet exceeding LMAX has been transmitted (TAB source).
This bit is not set to 1 if MACC.HUGEN = 1.
A late collision has been detected (TAB source).
Collisions have occurred exceeding the maximum number of collisions (TAB source).
An excessive transmission delay has been detected (TAB source).
A transmission delay has occurred.
The length field is greater than 1,500.
This bit is also set to 1 when a VLAN packet pause control frame is transmitted.
It is not set to 1 if MACC1.FLCHT = 0.
The length field does not match the data field length.
This bit is not set to 1 if MACC1.FLCHT = 0. A length field exceeding 1,500 is reported to TFLOR
and TFLER is not set to 1.
CRC error
This bit is set to 1 if transmission is performed with the CRC automatic appending mode disable
(MACC1.PADEN = 0 and CRCEN = 0).
30
22
14
R
R
R
R
0
0
0
6
ECOL
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
0
5
User’s Manual U19601EJ2V0UD
TEDFR
28
20
12
R
R
R
R
0
0
0
4
TDFR
27
19
11
R
R
R
R
0
0
0
3
Description
TFLOR
26
18
10
R
R
R
R
0
0
0
2
TFLER
25
17
R
R
R
R
0
0
9
0
1
TCRCE
TAB
24
16
R
R
R
R
0
8
0
0