UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 883

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.7 How to Use
(1) Single mode (in master mode and transmission mode)
(2) Single mode (in master mode and reception mode)
<1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled.
<2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers.
<3> Write 1 to the CEnSTR.CEnPCT bit to clear all the CSIBUFn pointers to 0.
<4> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<5> Specify the transfer mode by using the CEnCTL0.CEnTMS, CEnCTL0.CEnDIR, and CEnCTL0.CEnSIT
<6> Confirm that the CEnSTR.CEnFLF register is 0, and then write transfer data to the CEnTX0 register. If it
<7> Confirm that the INTCEnT interrupt has occurred and the CEnSTR.CEnEMF bit is 1, and disable
<1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled.
<2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers.
<3> Write 1 to the CEnSTR.CEnPCT bit to clear all the CSIBUFn pointers to 0.
<4> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<5> Specify the transfer mode by using the CEnCTL0.CEnTMS, CEnCTL0.CEnDIR, and CEnCTL0.CEnSIT
<6> Confirm that the CEnSTR.CEnFLF register is 0, and then write dummy transfer data to the CEnTX0
<7> Confirm that the INTCEnT interrupt has occurred, and then read the CEnRX0 register.
<8> Confirm that the INTCEnT interrupt has occurred and the CEnEMF bit is 1, and disable reception by
CEnSFP0 bits = 0000.
bits and, at the same time, enable transmission by setting the CEnTXE bit to 1.
is clearly known that the CEnFLF bit is 0 because transfer data is written to that bit by the interrupt
servicing routine of INTCEnT, it is not always necessary to confirm that the CEnFLF bit is 0.
transmission by clearing the CEnCTL0.CEnTXE bit to 0 (end of transmission).
Caution To execute further transfer, repeat <6> before <7>.
CEnSFP0 bits = 0000.
bits and, at the same time, enable reception by setting the CEnRXE bit to 1.
register (reception start trigger). If it is clearly known that the CEnFLF bit is 0 because dummy transfer
data is written to that bit by the interrupt servicing routine of INTCEnT, it is not always necessary to
confirm that the CEnFLF bit is 0.
clearing the CEnCTL0.CEnRXE bit to 0 (end of reception).
Cautions 1. To execute further transfer, repeat <6> and <7> before <8>.
2. The SOEn pin outputs a low level but this is invalid.
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD
881