UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 344

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
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7.8
set as capture registers (TAA0CCSn = 1).
(slave timer) to use them as a 32-bit capture timer by cascade connection.
342
[Lower timer TAA1]
This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer.
For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be
Combinations of TAA channels that can be connected in cascade are shown in the following table.
In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer
Capture signal 1
Capture signal 0
Cascade Connection
(TIAA11)
(TIAA10)
Operation enable
selection
Count
clock
bit (TAA1CE)
detection
detection
Edge
Edge
Lower capture interrupt 0
(INTTAA1CC0)
Lower Timer (Master Timer)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Lower capture interrupt 1
Lower capture register 1
Lower capture register 0
Lower timer counter
Figure 7-50. Cascade Connection Example
Table 7-11. Cascade Connection of TAA
(INTTAA1CC1)
(TAA1CCR1)
(TAA1CCR0)
TAA1
TAA3
User’s Manual U19601EJ2V0UD
Lower overflow interrupt
(INTTAA1OV)
detection
FFFFH
signal
Higher Timer (Slave Timer)
[Higher timer TAA0]
TAA0
TAA2
Higher capture register 0
Higher capture register 1
Higher timer counter
(TAA0CCR0)
(TAA0CCR1)
Higher overflow interrupt
(INTTAA0OV)

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