UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 746

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

744
Remark
For details of parity, see 16.7.6 Parity types and corresponding operation.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
UBnPS1
UBnDIR
•
•
•
Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnCL bit.
•
•
UBnCL
UBnSL
Clear the UBnPWR bit or UBnTXE and UBnRXE bits to 0 before rewriting the
UBnDIR bit.
Clear the UBnTXE and UBnRXE bits to 0 before overwriting the UBnPS1 and
UBnPS0 bits.
If “0 parity” is selected for reception, no parity judgment is made. Therefore, no
error interrupt is generated because the UBnSTR.UBnPE bit is not set to 1.
Clear the UBnTXE bit to 0 before overwriting the UBnSL bit.
Since reception always operates by using a single stop bit length, the UBnSL bit
setting does not affect receive operations.
0
1
0
1
0
0
1
1
0
1
1 bit
2 bits
MSB transfer first
LSB transfer first
7 bits
8 bits
UBnPS0
Specification of data character length of 1-frame transmit/receive data
0
1
0
1
Parity selection during transmission
Specification of transfer direction mode (MSB/LSB)
Do not output a parity bit
Output 0 parity
Output odd parity
Output even parity
Specification of stop bit length of transmit data
User’s Manual U19601EJ2V0UD
Receive with no parity
Receive as 0 parity
Judge as odd parity
Judge as even parity
Parity selection during reception
(2/2)