UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1503

no-image

UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
CHAPTER 23 ETHERNET CONTROLLER
(2) Setting address filtering conditions
Set address filtering as follows.
First, clear the MACC1.SRXEN bit to 0. When the SRXEN bit is set to 0, the receive data interface is disabled.
Next, set a terminal address to the LSA1 and LSA2 registers. A combination of the necessary filtering
conditions to the AFR register. To receive conditional multicast packets, a hash table must be set by using the
HT1 and HT2 registers.
After making the above setting, enable packet reception by setting the
MACC1.SRXEN bit to 1.
1501
User’s Manual U19601EJ2V0UD

Related parts for UPD70F3786GJ-GAE-AX