UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 263

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAAnIOC0
(c) TAAn I/O control register 0 (TAAnIOC0)
(d) TAAn counter read buffer register (TAAnCNT)
(e) TAAn capture/compare register 0 (TAAnCCR0)
(f) TAAn capture/compare register 1 (TAAnCCR1)
By reading the TAAnCNT register, the count value of the 16-bit counter can be read.
If the TAAnCCR0 register is set to D
Interval = (D
Usually, the TAAnCCR1 register is not used in the interval timer mode. However, the set value of the
TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal
(INTTAAnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1
buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TAAnCCMK1).
Remarks 1. TAAn I/O control register 1 (TAAnIOC1), TAAn I/O control register 2 (TAAnIOC2), and
0
Figure 7-9. Register Settings for Interval Timer Mode Operation (2/2)
2. n = 0 to 5
0
+ 1) × Count clock cycle
TAAn option register 0 (TAAnOPT0) are not used in the interval timer mode.
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
0
User’s Manual U19601EJ2V0UD
0
, the interval is as follows.
TAAnOL1
0/1
TAAnOE1 TAAnOL0 TAAnOE0
0/1
0/1
0/1
Setting of output level with
operation of TOAAn0 pin disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Setting of output level with
operation of TOAAn1 pin disabled
0: Low level
1: High level
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
261