UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 563

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.6.9
to TT0MD0 bits = 1000)).
The encoder count function includes an encoder compare mode (see 9.6.10 Encoder compare mode (TT0MD3
(1) Count-up/-down control
(2) Setting initial value of 16-bit counter
(3) Basic operation
(4) Clear operation
Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and
TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits.
When the encoder count function is used, the internal count clock and external event count input (TENC00)
cannot be used. Set the TT0CTL0.TT0CKS2 to TT0CTL0.TT0CKS0 bits to 000 and the TT0CTL1.TT0EEE bit
to 0.
The initial count value set to the TT0TCW register when the TT0CTL2.TT0ECC bit = 0 is transferred to the 16-
bit counter immediately after the counter starts its operation (TT0CTL0.TT0CE bit = 0 → 1), and the counter
starts the operation after it detects the valid edge of the encoder input signal (TENC00 or TENC01).
The TT0CCRn register generates a compare match interrupt request signal (INTTT0CCn) when the count
value of the 16-bit counter matches the value of the CCRn buffer register.
The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode.
• When the value of the 16-bit counter matches the value of the compare register (the TT0CTL2.TT0ECM1
• When the edge of the encoder clear input signal (TECR0) is detected (the TT0ECS1 and TT0ECS0 bits are
• When the clear level condition of the TENC00, TENC01, and TECR0 pins is detected (the TT0ZCL, TT0BCL,
Remark
Encoder count function
and TT0CTL2.TT0ECM0 bits are set)
set when the TT0IOC3.TT0SCE bit = 0)
and TT0ACL bits are set when the TT0SCE bit = 1)
Encoder compare mode
n = 0, 1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Mode
User’s Manual U19601EJ2V0UD
Compare only
TT0CCR0 Register
Compare only
TT0CCR1 Register
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