UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1574

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

25.3.2 Restore
address of the restored PC.
1572
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Note For the ISPR register, see 25.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt
Remark
0.
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR
instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
1
PC
PSW
Corresponding
bit of ISPR
CHAPTER 25 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Restores original processing
RETI instruction
Note
Figure 25-6. RETI Instruction Processing
PSW.EP
PSW.NP
0
0
EIPC
EIPSW
0
User’s Manual U19601EJ2V0UD
1
PC
PSW
FEPC
FEPSW