UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 763

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6 Control Modes
(1) Single mode/FIFO mode
The single mode or FIFO mode can be selected by using the UBnFIC0.UBnMOD bit.
(a) Single mode
(b) FIFO mode
• Each of the UBnRX and UBnTX registers consists of 8 bits × 1 stage.
• When 1 byte of data is received, the INTUBnTIR signal is generated.
• If the next reception operation of UARTBn is ended before the receive data of the UBnRX register is
• Receive FIFO (UBnRXAP register) consists of 16 bits × 16 stages and transmit FIFO consists of 8 bits
• Receive FIFO can recognize error data by reading the 16-bit UBnRXAP register only when a reception
• Transmission is started when transmission is enabled (UBnCTL0.UBnTXE bit = 1) after transmit data
• The pending mode or pointer mode can be selected for the generation timing of the INTUBnTIT and
Remark
read after the INTUBnTIR signal has been generated, the INTUBnTIRE signal is generated and an
overrun error occurs.
× 16 stages.
error (parity error or framing error) occurs.
of at least the number set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16
bytes or less are written to transmit FIFO.
INTUBnTIR signals.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
n = 0, 1
User’s Manual U19601EJ2V0UD
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