UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 744

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 Control Registers
742
(1) UARTBn control register 0 (UBnCTL0)
Remarks 1. When reception is disabled, the receive shift register does not detect a start bit. No shift-in
The UBnCTL0 register controls the transfer operations of UARTBn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
Cautions 1. When using UARTBn, set the external pins related to the UARTBn function in the
2. Be sure to input a high level to the RXDBn pin when setting the external pins related to
2. n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
processing or transfer processing to the receive data register is performed, and the contents of
the receive data register are retained.
When reception is enabled, the receive shift operation starts, in synchronization with the
detection of the start bit, and when the reception of one frame is completed, the contents of the
receive shift register are transferred to the receive data register.
A reception end interrupt request signal (INTUBnTIR) is also generated, in synchronization
with the transfer to the receive data register (in FIFO mode, transfer triggered by reaching set
number of receive data).
If data is stored in receive FIFO when the next data does not come (start bit is not detected)
after the next data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0
bits has elapsed in the FIFO mode, a reception timeout interrupt request signal (INTUBnTITO)
is generated.
alternate-function mode, set UARTBn control register 2 (UBnCTL2).
UBnPWR bit to 1 before setting the other bits.
the UARTBn function in the alternate-function mode. If a low level is input, it is judged
that a falling edge is input after the UBnRXE bit has been set to 1, and reception may be
started.
User’s Manual U19601EJ2V0UD
Then set the