UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1524

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

After the RXS bit of the core function setting register (ETHMODE) is set to 1 by software, the first descriptor is read
from the address indicated by the reception descriptor pointer (RXDP) (0028 0000H), and the reception descriptor is
analyzed.
the FIFO is transferred to buffer A.
address pointer (0028 1800H) is set as the DMA start address, and the reception data in the FIFO is transferred to
buffer C.
written back to the descriptor’s size field.
reception status information is written back to the status (A) field.
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How reception works is described below using an example of an actual descriptor chain.
The first buffer address pointer (0028 1000H) is set as the DMA transfer start address and the reception data in
When buffer A becomes full upon subsequent receptions, the next descriptor (0028 0008H) is read, the buffer
In the final reception, the E and U bits of the descriptor are set to 1, and the number of data bytes transferred is
Once all the packet data has been transferred, the U and S bits of the first descriptor are set to 1, and the
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD