UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 822

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

820
LIN
bus
RXDCn (input)
Edge detection
Notes 1. The wakeup signal is sent by the pin edge detector, UARTCn is enabled, and the SBF reception
Remark
2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
4. The RXDCn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the
5. Check-sum field distinctions are made by software. UARTC is initialized following CSF reception,
mode is set.
of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon
detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal
is output, and the mode returns to the SBF reception mode.
reception
UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART communication error detection
processing and UARTCn receive shift register and data transfer of the UCnRX register are not
performed. The UARTCn receive shift register holds the initial value, FFH.
baud rate error is calculated. The value of the UCnCTL2 register obtained by correcting the baud
rate error after dropping UARTC enable is set again, causing the status to become the reception
status.
and the processing for setting the SBF reception mode again is performed by software.
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
Reception interrupt (INTUCnR)
Capture timer
Disable
Wake-up
signal
frame
completion
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Enable
Note 1
Figure 17-12. LIN Reception Manipulation Outline
Disable
interrupt.
reception
Note 2
13 bits
break
SBF
Sync
field
User’s Manual U19601EJ2V0UD
Note 3
Enable
Moreover,
SF reception
Sync
field
Note 4
error
ID reception
Identifier
field
detection
transmission
DATA
Data
field
for
the
transmission
Data
DATA
UCnSTR.UCnOVE,
field
Data transmission
Check
SUM
Note 5
field