MC68030RC33 Motorola, MC68030RC33 Datasheet

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MC68030RC33

Manufacturer Part Number
MC68030RC33
Description
MC68030RC33ENHANCED 32-BIT MICROPROCESSOR
Manufacturer
Motorola
Datasheet
查询MC68030FE20供应商
MOTOROLA
MC68030
ENHANCED 32-BIT
MICROPROCESSOR
USER’S MANUAL
Third Edition
MOTOROLA INC., 1992

Related parts for MC68030RC33

MC68030RC33 Summary of contents

Page 1

... MOTOROLA MC68030 ENHANCED 32-BIT MICROPROCESSOR USER’S MANUAL Third Edition MOTOROLA INC., 1992 ...

Page 2

... The audience of this manual includes systems designers, systems programmers, and applications programmers. Systems designers need some knowledge of all sections, with particular emphasis on Sections 13, 14, and Appendix A. Designers who implement a coprocessor for their system also need a thorough knowledge of Section 10. MOTOROLA NOTE MC68030 USER’S MANUAL xxiii ...

Page 3

... Family members and those who are not familiar with these microprocessors. Users of the other family members can find references to similarities to and differences from the other Motorola microprocessors throughout the manual. However, Section 1 and Appendix A specifically identify the MC68030 within the rest of the family and contrast its differences. ...

Page 4

... Program Counter Indirect with Index (Base Displacement) Mode. . 2-17 2.4.14 Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . 2-18 2.4.15 Program Counter Memory Indirect Preindexed Mode . . . . . . . . . . . 2-19 2.4.16 Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.17 Absolute Long Addressing Mode 2-20 2.4.18 Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.5 Effective Address Encoding Summary . . . . . . . . . . . . . . . . . . . . . . . . 2-22 MOTOROLA TABLE OF CONTENTS Title Section 1 Introduction Section 2 MC68030 USER’S MANUAL Page Number xxv ...

Page 5

... Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.5.4 Pipeline Synchronization with the Nop Instruction 3-32 4.1 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 Supervisor Privilege Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 User Privilege Level 4-3 4.1.3 Changing Privilege Level 4-4 4.2 Address Space Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 Exception Processing 4-6 xxvi Title Section 3 Instruction Set Summary Section 4 Processing States MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 6

... Bus Grant Acknowledge (BGACK 5-9 5.10 Bus Exception Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.10.1 Reset (RESET 5-9 5.10.2 Halt (HALT 5-9 5.10.3 Bus Error (BERR 5-9 5.11 Emulator Support Signals 5-10 5.11.1 Cache Disable (CDIS 5-10 5.11.2 MMU Disable (MMUDIS 5-10 5.11.3 Pipeline Refill (REFILL 5-10 5.11.4 Internal Microsequencer Status (STATUS 5-10 MOTOROLA Title Section 5 Signal Description MC68030 USER’S MANUAL Page Number xxvii ...

Page 7

... Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.2 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.3 Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.4 Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.5 Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.6 Data Buffer Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.1.7 Bus Cycle Termination Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2 Data Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.1 Dynamic Bus Sizing 7-6 xxviii Title Section 6 On-Chip Cache Memories Section 7 Bus Operation MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 8

... Double Bus Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-94 7.6 Bus Synchronization 7-95 7.7 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-96 7.7.1 Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-98 7.7.2 Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99 7.7.3 Bus Grant Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-100 7.7.4 Bus Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-100 7.8 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-103 8.1 Exception Processing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Reset Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.1.2 Bus Error Exception 8-7 MOTOROLA Title Section 8 Exception Processing MC68030 USER’S MANUAL Page Number xxix ...

Page 9

... Long-Fomat Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 9.5.1.5 Short-Format Early Termination Page Descriptor . . . . . . . . . . . . 9-25 9.5.1.6 Long-Format Early Termination Page Descriptor . . . . . . . . . . . . 9-25 9.5.1.7 Short-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.5.1.8 Long-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.5.1.9 Short-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.5.1.10 Long-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.5.1.11 Short-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 xxx Title Section 9 Memory Management Unit MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 10

... Initial Shift Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-69 9.9.3.3 Limit Fields 9-70 9.9.3.4 Early Termination Page Descriptors . . . . . . . . . . . . . . . . . . . . . . 9-70 9.9.3.5 Indirect Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-71 9.9.3.6 Using Unused Descriptor Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-71 9.10 An Example of Paging Implementation in an Operating System . . . . 9-72 9.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-72 9.10.2 Allocation Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-78 9.10.3 Bus Error Handler Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-82 xxxi Title Section 10 Coprocessor Interface Description MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 11

... Not Ready Format Word 10-23 10.2.3.2.3 Invalid Format Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.2.3.2.4 Valid Format Word 10-24 10.2.3.3 Coprocessor Context Save Instruction . . . . . . . . . . . . . . . . . . . . 10-24 10.2.3.3.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.2.3.3.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.2.3.4 Coprocessor Context Restore Instruction 10-27 10.2.3.4.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.2.3.4.2 Protocol 10-28 10.3 Coprocessor Interface Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.3.1 Response CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.3.2 Control CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.3.3 Save CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 xxxii Title MC68030 USER’S MANUAL Page Number MOTOROLA ...

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... Coprocessor-Detected Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 10-61 10.5.1.1 Coprocessor-Detected Protocol Violations . . . . . . . . . . . . . . . . . 10-62 10.5.1.2 Coprocessor-Detected Illegal Command or Condition Words . . . 10-63 10.5.1.3 Coprocessor Data-Processing Exceptions . . . . . . . . . . . . . . . . . 10-63 10.5.1.4 Coprocessor System-Related Exceptions . . . . . . . . . . . . . . . . . . 10-64 10.5.1.5 Format Errors 10-64 10.5.2 Main-Processor-Detected Exceptions . . . . . . . . . . . . . . . . . . . . . . . 10-65 10.5.2.1 Protocol Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65 10.5.2.2 F-Line Emulator Exceptions 10-68 10.5.2.3 Privilege Violations 10-69 10.5.2.4 cpTRAPcc Instruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69 10.5.2.5 Trace Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70 MOTOROLA Title MC68030 USER’S MANUAL Page Number xxxiii ...

Page 13

... Special-Purpose Move Instruction 11-39 11.6.8 Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11.6.9 Immediate Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . 11-42 11.6.10 Binary-Coded Decimal and Extended Instructions . . . . . . . . . . . . . 11-43 11.6.11 Single Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.6.12 Shift/Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.6.13 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.6.14 Bit Field Manipulation Instructions 11-47 11.6.15 Conditional Branch Instructions 11-48 xxxiv Title Section 11 Instruction Execution Timing MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 14

... External Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.6.1 Cache Implementation 12-32 12.6.2 Instruction-Only External Cache Implementations . . . . . . . . . . . . . 12-35 12.7 Debugging Aids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 12.7.1 Status and Refill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12.7.2 Real-Time Instruction Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.8 Power and Ground Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 13.1 Maximum Ratings 13-1 13.2 Thermal Characteristics — PGA Package . . . . . . . . . . . . . . . . . . . . . 13-1 MOTOROLA Title Section 12 Applications Information Section 13 Electrical Characteristics MC68030 USER’S MANUAL Page Number xxxv ...

Page 15

... Paragraph Number 14.1 Standard MC68030 Ordering Information . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 Pin Assignments — Pin Grid Array (RC Suffix 14-2 14.3 Pin Assignments — Ceramic Surface Mount (FE Suffix 14-3 14.4 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 xxxvi Title Section 14 Ordering Information and Mechanical Data Appendix A M68000 Family Summary MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 16

... Single Entry Mode Operation — Misaligned Long Word and 8-Bit Port 6-13 6-9 Single Entry Mode Operation — Misaligned Long Word and 16-Bit Port. . 6-14 6-10 Single Entry Mode Operation — Misaligned Long Word and 32-Bit DSACKx Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 MOTOROLA LIST OF ILLUSTRATIONS Title MC68030 USER’S MANUAL Page Number ...

Page 17

... Instruction with CIOUT or CIIN Asserted 7-45 7-31 Synchronous Long-Word Read Cycle Flowchart — No Burst Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 7-32 Synchronous Read with CIIN Asserted and CBACK Negated . . . . . . . . . . 7-50 7-33 Synchronous Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52 7-34 Synchronous Write Cycle with Wait States — CIOUT Asserted . . . . . . . . 7-53 xxxviii Title MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 18

... Initial Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-105 7-65 Processor-Generated Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-106 8-1 Reset Operation Flowchart 8-6 8-2 Interrupt Pending Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8-3 Interrupt Recognition Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8-4 Assertion of IPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8-5 Interrupt Exception Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8-6 Examples of Interrupt Recognition and Instruction Boundaries . . . . . . . . . 8-20 8-7 Breakpoint Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 MOTOROLA Title MC68030 USER’S MANUAL Page Number xxxix ...

Page 19

... Exmple Logical Address Map with Shared Supervisor and User Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49 9-34 Exmple Translation Tree Using S and WP Bits to Set Protection . . . . . . . 9-50 9-35 Root Pointer Register (CRP, SRP) Format . . . . . . . . . . . . . . . . . . . . . . . . 9-54 9-36 Translation Control Register (TC) Format . . . . . . . . . . . . . . . . . . . . . . . . . 9-54 9-37 Transparent Translation Register (TT0 and TT1) Format . . . . . . . . . . . . . 9-57 xl Title MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 20

... Transfer To/From Top of Stack Primitive Format . . . . . . . . . . . . . . . . . . . . 10-49 10-33 Transfer Single Main Processor Register Primitive Format . . . . . . . . . . . . 10-50 10-34 Transfer Main Processor Control Register Primitive Format . . . . . . . . . . . 10-51 10-35 Transfer Multiple Main Processor Registers Primitive Format . . . . . . . . . . 10-52 10-36 Register Select Mask Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52 10-37 Transfer Multiple Coprocessor Registers Primitive Format . . . . . . . . . . . . 10-53 MOTOROLA Title MC68030 USER’S MANUAL Page Number xli ...

Page 21

... Additional Memory Enable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12-17 Example MC68030 Hardware Configuration with External Physical Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33 12-18 Example Early Termination Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . 12-34 12-19 Normal Instruction Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12-20 Trace or Interrupt Exception 12-38 12-21 Other Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 12-22 Processor Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12-23 Trace Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41 12-24 PAL Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44 12-25 Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45 xlii Title MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 22

... DSACK, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-79 7-8 7-9 STERM, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-81 8-1 Exception Vector Assignments (Sheet 8-2 8-2 Exception Vector Assignments (Sheet 8-3 8-3 Microsequencer STATUS Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8-4 Tracing Control 8-13 8-5 Interrupt Levels and Mask Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8-6 Exception Priority Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 MOTOROLA LIST OF TABLES Title MC68030 USER’S MANUAL Page Number xliii ...

Page 23

... Memory Access Time Equations at 20 MHz . . . . . . . . . . . . . . . . . . . . . . . 12-16 12-3 Calculated t AVDV Less Than or Equal to the CPU Maximum Frequency Rating . . . . . . . . . 12-17 12-4 Microsequencer STATUS Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12-5 List of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12-6 AS and ECSC Indicates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12-7 V and GND Pin Assignments 12-46 CC xliv Title Values for Operation at Frequencies MC68030 USER’S MANUAL Page Number MOTOROLA ...

Page 24

... SECTION 1 INTRODUCTION The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola. The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit (MMU single VLSI device. The processor is designed to operate at clock speeds beyond 20 MHz ...

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... Introduction 1-2 Figure 1-1. Block Diagram MC68030 USER’S MANUAL MOTOROLA ...

Page 26

... Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coproces- sors • 4-Gbyte Logical and Physical Addressing Range • Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High- Density NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum Die Size • Processor Speeds Beyond 20 MHz Both improved performance and increased functionality result from the on-chip implementation of the MMU and the data and instruction caches ...

Page 27

... This corresponds to the user and supervisor privilege levels. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions. 1-4 MC68030 USER’S MANUAL MOTOROLA ...

Page 28

... MC68030 is new to the family supervisor programming model for the MC68030 and the two translation registers are new additions to the family supervisor programming model for the MC68030. Only supervisor code uses this feature, and user application programs remain unaffected. MOTOROLA MC68030 USER’S MANUAL Introduction 1-5 ...

Page 29

... All of the 16 general-purpose registers (D0–D7, A0–A7) may be used as index registers Figure 1-2. User Programming Model 1 MC68030 USER’S MANUAL DATA REGISTERS ADDRESS A3 REGISTERS USER STACK A7 (USP) POINTER 0 PROGRAM PC COUNTER 0 CONDITION CODE CCR REGISTER MOTOROLA ...

Page 30

... One of two trace modes (T1, T0) 2. Supervisor or user privilege level (S) 3. Master or interrupt mode (M) The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. MOTOROLA ...

Page 31

... This feature is useful to graphics, controller, and real-time applications. 1-8 USER BYTE (CONDITION CODE REGISTER INTERRUPT PRIORITY MASK Figure 1-4. Status Register MC68030 USER’S MANUAL CARRY OVERFLOW ZERO NEGATIVE EXTEND MOTOROLA ...

Page 32

... The instructions in the MC68030 instruction set are listed in Table 1-2. The instruction set has been tailored to support structured high-level languages and sophisticated operating systems. Many instructions operate on bytes, words, or long words, and most instructions can use any of the 18 addressing modes. MOTOROLA MC68030 USER’S MANUAL Introduction 1-9 ...

Page 33

... Immediate value bits ( ) = Effective Address [ ] = Use as indirect access to long-word address. 1-10 Table 1-1. Addressing Modes Dn An (An) (An) –(An ,An,Xn) 8 (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d ,PC ,PC,Xn) 8 (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #(data bits; when omitted, assemblers use a value of zero MC68030 USER’S MANUAL Syntax ,An) MOTOROLA ...

Page 34

... When the bus error handler has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction. MOTOROLA MC68030 USER’S MANUAL Introduction ...

Page 35

... Return and Restore Codes Return from Subroutine Subtract Decimal With Extend Set Conditionally Stop Subtract Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test on Overflow Test Operand Unlink Unpack BCD MOTOROLA ...

Page 36

... Instruction continuation is used to support virtual I/O devices in memory-mapped input/ output systems. Control and data registers for the virtual device are simulated in the memory map. An access to a virtual register causes a fault and the function of the register is emulated by software. MOTOROLA Mnemonic cpRESTORE cpSAVE cpScc cpTRAPcc MC68030 USER’ ...

Page 37

... The logical address space is divided into fixed-size pages that contain the same number of bytes as the page frames. Memory management assigns a physical base address to a logical page. The system software then transfers data between secondary storage and memory one or more pages at a time. 1-14 MC68030 USER’S MANUAL MOTOROLA ...

Page 38

... However, writing data that is not in the cache may or may not cause the data item to be stored in the cache, depending on the write allocation policy selected in the cache control register (CACR). MOTOROLA MC68030 USER’S MANUAL Introduction 1-15 ...

Page 39

... Coprocessors are designed to support special computation models that require very specific but widely varying data operand types and sizes. Hence, coprocessor instructions can specify operands of any size. MOTOROLA MC68030 USER’S MANUAL 2-1 ...

Page 40

... BCD format, a byte contains one digit; the four least significant bits contain the binary value and the four most significant bits are undefined. Each byte of the packed BCD format contains two digits; the least significant four bits contain the least significant digit. 2-2 MC68030 USER’S MANUAL MOTOROLA ...

Page 41

... Offset<32, 0<Width 31 Note: If width + offset < 32, bit filed wraps around within the register. Unpacked BCD (a = MSB) 31 Packed BCD (a = MSB First Digit MSB Second Digit) 31 Data Organization in Data Registers MOTOROLA Data Organization and Addressing Capabilities 16 15 Middle-High Byte Middle-Low Byte 16 15 Long Word ...

Page 42

... The status register (SR), shown in Figure 1– bits wide. Only 12 bits of the status register are defined; all undefined values are reserved by Motorola for future definition. The undefined bits are read as zeros and should be written as zeros for future compatibility. The lower byte of the status register is the CCR ...

Page 43

... MC68030 does not require data to be aligned on word boundaries (refer to Figure 2–2), but the most efficient data transfers occur when data is aligned on the same byte boundary as its operand size. However, instruction words must be aligned on word boundaries. MOTOROLA Data Organization and Addressing Capabilities MC68030 USER’S MANUAL 2-5 ...

Page 44

... Figure 2-1. Memory Operand Address 2-6 15 LONG WORD $00000000 BYTE $00000001 BYTE $00000002 LONG WORD $00000004 WORD $00000006 BYTE $00000005 BYTE $00000006 LONG WORD $FFFFFFFC WORD $FFFFFFFE BYTE $FFFFFFFD BYTE $FFFFFFFE MC68030 USER’S MANUAL 7 0 WORD $00000002 BYTE $00000003 BYTE $00000007 BYTE $FFFFFFFF MOTOROLA ...

Page 45

... BYTE BYTE ADDRESS ADDRESS BYTE USER DEFINED VALUE Figure 2-2. Memory Data Organization MOTOROLA Data Organization and Addressing Capabilities BIT DATA BYTE BASE ADDRESS BIT NUMBER BIT FIELD DATA BYTE ...

Page 46

... Many instructions imply the addressing mode for one of the operands. The formats of these instructions include appropriate fields for operands that use only one addressing mode. 2 MC68030 USER’S MANUAL –1, and bit field 0 EFFECTIVE ADDRESS MODE REGISTER MOTOROLA ...

Page 47

... Data Register Direct Mode In the data register direct mode, the operand is in the data register specified by the effective address register field. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: DATA REGISTER: NUMBER OF EXTENSION WORDS: MOTOROLA Data Organization and Addressing Capabilities 000 OPERAND 0 MC68030 USER’ ...

Page 48

... MODE: REGISTER: ADDRESS REGISTER: OPERAND LENGTH ( 4): MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2- 001 (An) (An) 010 MEMORY ADDRESS (An SIZE (An) + 011 31 n MEMORY ADDRESS MC68030 USER’S MANUAL 0 OPERAND 0 0 OPERAND 0 0 OPERAND MOTOROLA ...

Page 49

... GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: OPERAND LENGTH ( 4): MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 0 MOTOROLA Data Organization and Addressing Capabilities – SIZE EA = (An) – (An) 100 31 n MEMORY ADDRESS An 31 MC68030 USER’ ...

Page 50

... MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2- (An ,An) 16 101 MEMORY ADDRESS 15 0 INTEGER (An) + (XN ,An,Xn.SIZE*SCALE) 8 110 SIGN EXTENDED INTEGER 0 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE 31 1 MC68030 USER’S MANUAL OPERAND 0 MEMORY ADDRESS + + X 0 OPERAND MOTOROLA ...

Page 51

... GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: ADDRESS REGISTER: 31 BASE DISPLACEMENT: 31 INDEX REGISTER: SCALE: MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA Data Organization and Addressing Capabilities EA = (An) + (Xn (bd,An,Xn.SIZE*SCALE) 110 SIGN-EXTENDED VALUE 0 SIGN-EXTENDED VALUE 7 ...

Page 52

... OUTER DISPLACEMENT: EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: 2- (bd + An) + Xn.SIZE*SCALE + od ([bd,An],Xn.SIZE*SCALE,od) 31 110 An 0 SIGN-EXTENDED VALUE 31 INDIRECT MEMORY ADDRESS 31 VALUE AT INDIRECT MEMORY ADDRESS 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE 0 SIGN-EXTENDED VALUE 31 1, MC68030 USER’S MANUAL 0 MEMORY ADDRESS + 0 POINTS OPERAND MOTOROLA ...

Page 53

... GENERATION: ASSEMBLER SYNTAX: MODE: ADDRESS REGISTER: 31 BASE DISPLACEMENT: 31 INDEX REGISTER: SCALE: 31 OUTER DISPLACEMENT: EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA Data Organization and Addressing Capabilities Xn.SIZE*SCALE ([bd,An,Xn.SIZE*SCALE],od) 31 110 An 0 SIGN-EXTENDED VALUE 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE ...

Page 54

... NUMBER OF EXTENSION WORDS: 2- (PC ,PC) 16 111 31 010 ADDRESS OF EXTENSION WORD 0 15 INTEGER (PC) + (Xn PC,Xn. SIZE*SCALE) 8 111 31 011 ADDRESS OF EXTENSION WORD 7 0 SIGN EXTENDED INTEGER 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE 31 1 MC68030 USER’S MANUAL OPERAND OPERAND MOTOROLA ...

Page 55

... ZPC in the instruction and specifying a data register (Dn) as the index register. GENERATION: ASSEMBLER SYNTAX: MODE: REGISTER: PROGRAM COUNTER: 31 BASE DISPLACEMENT: 31 INDEX REGISTER SCALE: MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: MOTOROLA Data Organization and Addressing Capabilities EA = (PC) + (Xn (bd, PC, Xn. SIZE*SCALE) 111 31 011 ADDRESS OF EXTENSION WORD 0 SIGN-EXTENDED VALUE 0 SIGN-EXTENDED VALUE 7 0 ...

Page 56

... EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS: 2- (bd + PC) + Xn.SIZE*SCALE + od ([bd, PC], Xn.SIZE*SCALE,od) 111 31 011 0 SIGN-EXTENDED VALUE 31 INDIRECT MEMORY ADDRESS 31 VALUE AT INDIRECT MEMORY ADDRESS IN PROGRAM SPACE 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE 0 SIGN-EXTENDED VALUE 31 1, MC68030 USER’S MANUAL 0 MEMORY ADDRESS + 0 POINTS OPERAND MOTOROLA ...

Page 57

... MODE: 111 REGISTER FIELD: 011 PROGRAM COUNTER: 31 BASE DISPLACEMENT: 31 INDEX REGISTER 31 OUTER DISPLACEMENT: EFFECTIVE ADDRESS: NUMBER OF EXTENSION WORDS MOTOROLA Data Organization and Addressing Capabilities 31 ADDRESS OF EXTENSION WORD 0 SIGN-EXTENDED VALUE 0 SIGN-EXTENDED VALUE 7 0 SCALE VALUE 31 INDIRECT MEMORY ADDRESS 31 VALUE AT INDIRECT MEMORY ...

Page 58

... REGISTER FIELD: FIRST EXTENSION WORD: SECOND EXTENSION WORD: MEMORY ADDRESS: NUMBER OF EXTENSION WORDS: 2-20 EA GIVEN (xxx).W 111 31 000 SIGN EXTENDED GIVEN (xxx).L 111 15 001 ADDRESS HIGH 31 CONCATENATION 31 2 MC68030 USER’S MANUAL 15 0 MEMORY ADDRESS 0 OPERAND ADDRESS LOW 0 0 OPERAND MOTOROLA ...

Page 59

... Coprocessor instructions can support immediate data of any size. The instruction word is followed by as many extension words as are required. Generation: Assembler Syntax: Mode Field: Register Field: Number of Extension Words: MOTOROLA Data Organization and Addressing Capabilities Operand given #xxx 111 100 except for coprocessor instructions MC68030 USER’ ...

Page 60

... Indirect Postindexed with Mull Outer Displacement Indirect Postindexed with Word Outer Displacement Indirect Postindexed with Long Outer Displacement No Memory Indirection Memory Indirect with Mull Outer Displacement Memory Indirect with Word Outer Displacement Memory Indirect with Long Outer Displacement Reserved MC68030 USER’S MANUAL MOTOROLA ...

Page 61

... A memory addressing effective address mode is one that refers to memory operands. Alterable An alterable addressing effective address mode is one that refers to alterable (writable) operands. Control A control addressing effective address mode is one that refers to memory operands without an associated size. MOTOROLA Data Organization and Addressing Capabilities ...

Page 62

... MC68030 USER’S MANUAL Assembler Control Alterable Syntax — — (An) — X (An)+ — X -(An ,An ,An,Xn (bd,An,Xn ([bd,An],Xn,od ([bd,An,Xn],od (xxx). (xxx).L X — (d ,PC — (d ,PC,Xn — (bd,PC,Xn) X — ([bd,PC],Xn,od) X — ([bd,PC,Xn],od) — — # data MOTOROLA ...

Page 63

... Using the SIZE parameter, either the entire contents of the index register can be used, or the least significant word can be sign-extended to provide a 32-bit index value (refer to Figure 2–5). 31 D1.L 31 D1.W USED IN ADDRESS CALCULATION Figure 2-5. Using SIZE in the Index Selection MOTOROLA Data Organization and Addressing Capabilities 16 15 MC68030 USER’S MANUAL 2-25 ...

Page 64

... Another variation that can be derived is (An,Rn*scale). In the first case, the array address is the sum of the contents of a register and a displacement, as shown in Figure 2–7. In the second example. An contains the address of an array and Rn contains a subscript. 2-26 SYNTAX (bd,An,Rn MC68030 USER’S MANUAL MOTOROLA ...

Page 65

... RECORD OF 4 WORDS (SCALE = NOTE: Regardless of array structure, software increments index by the appropriate amount to point to next record. Figure 2-7. Addressing Array Items MOTOROLA Data Organization and Addressing Capabilities SYNTAX: MOVE.W (A5, A6.L*SCALE),(A7) WHERE ADDRESS OF ARRAY STRUCTURE A6 = INDEX NUMBER OF ARRAY ITEM A7 = STACK POINTER 0 ...

Page 66

... The actual data item is at the address in the selected pointer. The preindexed indirect mode (see Figure 2–11) uses the contents index to the pointer list structure at the displacement. Register Xn is the index to the pointer, which contains the address of the data item. 2-28 SYNTAX: ([bd]) MC68030 USER’S MANUAL DATA ITEM MOTOROLA ...

Page 67

... An Figure 2-9. Accessing an Item in a Structure Using a Pointer POINTER LIST bd POINTER Figure 2-10. Indirect Addressing, Suppressed Index Register MOTOROLA Data Organization and Addressing Capabilities SYNTAX: ([An],od) MEMORY POINTER SYNTAX: ([bd,An]) An MC68030 USER’S MANUAL STRUCTURE od DATA ITEM DATA ITEM 2-29 ...

Page 68

... Data Organization and Addressing Capabilities POINTER LIST bd POINTER Figure 2-11. Preindexed Indirect Addressing 2-30 SYNTAX: ([bd,An,Xn MC68030 USER’S MANUAL DATA ITEM MOTOROLA ...

Page 69

... Figure 2–13 shows the preindexed indirect addressing with outer displacement mode. POINTER LIST bd POINTER Figure 2-12. Postindexed Indirect Addressing POINTER LIST bd POINTER Figure 2-13. Preindexed Indirect Addressing with Outer Displacement MOTOROLA Data Organization and Addressing Capabilities SYNTAX: ([bd,An],Xn) An SYNTAX: ([bd,An,Xn],od MC68030 USER’S MANUAL POSTINDEXED STRUCTURE Xn ...

Page 70

... SYNTAX: ([bd,An],Xn,od) An MC68030 USER’S MANUAL POSTINDEXED STRUCTURE WITH OUTER DISPLACEMENT od Xn DATA ITEM ,An) is used. When a 32- 16 MOTOROLA ...

Page 71

... The data is a constant located in the instruction stream. Register Direct — Rn: The contents of a register contain the operand. Scanning Modes: (An)+ MOTOROLA Data Organization and Addressing Capabilities — Absolute address in data space — Register pointer with constant displacement — Register pointer with constant displacement — ...

Page 72

... Absolute address with two variable indexes. Subscripting: (An,Rn*scale) Address register pointer subscript. (disp,An,Rn*scale) Address register pointer subscript with constant displacement (or base address with subscript). (addr,Rn*scale) Absolute address with subscript. (addr,An,Rn*scale) Absolute address subscript with variable index. Program Relative: 2-34 MC68030 USER’S MANUAL MOTOROLA ...

Page 73

... Memory pointer as base with displacement to data operand. ([postindexed],Rn) Memory pointer with variable index. ([postindexed],disp,Rn) Memory pointer with constant and variable index. ([postindexed],Rn*scale) Memory pointer subscripted. ([postindexed],disp,Rn*scale) Memory pointer subscripted with constant index. MOTOROLA Data Organization and Addressing Capabilities MC68030 USER’S MANUAL 2-35 ...

Page 74

... M bit. When the term SSP (or A7) refers to the MSP address register. When the term is implicitly referenced by all instructions that use the system stack. Each system stack fills from high to low memory. 2-36 MC68030 USER’S MANUAL MOTOROLA ...

Page 75

... In long-word-organized memory, aligning the stack pointer on a long-word address signed significantly increases the efficiency of stacking exception frames, subroutine calls and returns, and other stacking operations. MOTOROLA Data Organization and Addressing Capabilities MC68030 USER’S MANUAL 2-37 ...

Page 76

... For this type of stack, after either a push or a pull operation, register An points to the top item on the stack. This is illustrated as: To implement stack growth from low to high memory, use: (An)+ to push data on the stack, –An to pull data from the stack. 2-38 LOW MEMORY An (FREE) TOP OF STACK BOTTOM OF STACK HIGH MEMORY MC68030 USER’S MANUAL MOTOROLA ...

Page 77

... To implement the queue as a circular buffer, the relevant address register should be checked and adjusted, if necessary, before performing the "put'' or "get'' operation. The address register is adjusted by subtracting the buffer length (in bytes) from the register. MOTOROLA Data Organization and Addressing Capabilities LOW MEMORY ...

Page 78

... The address register is adjusted by adding the buffer length (in bytes) to the register contents. 2-40 LOW MEMORY (FREE) LAST PUT NEXT GET LAST GET (FREE) HIGH MEMORY MC68030 USER’S MANUAL MOTOROLA ...

Page 79

... IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION( Figure 3-1. Instruction Word General Format MOTOROLA OPERATION WORD(ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IF ANY, ONE TO SIX WORDS) ...

Page 80

... The instructions form a set of tools to perform the following operations: Data Movement Integer Arithmetic Logical Shift and Rotate Bit Manipulation Each instruction type is described in detail in the following paragraphs 3-2 Bit Field Manipulation Binary-Coded Decimal Arithmetic Program Control System Control Multiprocessor Communications MC68030 USER’S MANUAL MOTOROLA ...

Page 81

... D3 — data = immediate data; a literal integer {offset:width} = bit field selection label = assemble program label [m] = bit operand [m:n] = bits m through n of operand MOTOROLA is a 16-bit displacement 16 MC68030 USER’S MANUAL Instruction Set Summary 3-3 ...

Page 82

... MOVE instructions, there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). 3-4 MC68030 USER’S MANUAL MOTOROLA ...

Page 83

... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extended (EXT), and negate binary with extend (NEGX). Refer to Table 3–2 for a summary of the integer arithmetic operations. MOTOROLA Operand Size ...

Page 84

... X 8, 16, 32 destination = source 8, 16 16, 32 destination - immediate data 8, 16 16, 32 destination - source — 16, 32 MC68030 USER’S MANUAL Operation destination destination destination destination (signed or unsigned) destination destination (signed or unsigned) destination destination destination destination MOTOROLA ...

Page 85

... SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 3– summary of the shift and rotate operations. MOTOROLA Table 3-3. Logical Operations Operand Size ...

Page 86

... Register operands are 32 bits long, and memory operands are 8 bits long. In Table 3–5, the summary of the bit manipulation operations, Z refers to bit 2, the zero bit of the status register. 3-8 0 X/C X MSW LSW MC68030 USER’S MANUAL C MOTOROLA ...

Page 87

... BFFFO ea {offset:width},Dn BFINS Dn, ea {offset:width} BFSET ea {offset:width} BFTST ea {offset:width} NOTE: All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operation. MOTOROLA Operand Size bit number of destination bit number of destination — 0 ...

Page 88

... Operand Size 8 source + destination destination – unpackaged source + immediate data destination destination - source packed source unpacked source unpacked source + immediate data 8 16 unpacked destination MC68030 USER’S MANUAL Operation + X destination 10 destination packed – X destination 10 MOTOROLA ...

Page 89

... Equal MI — Minus F — Never true* NE — Not equal *Not applicable to the Bcc instructions. MOTOROLA Operand Size Integer and Floating-Point Conditional 8, 16 condition true, then condition false, then Dn — -1, then condition true, then 1's else 0's ...

Page 90

... V, then take overflow TRAP exception Condition Code Register 8 immediate data 8 immediate data 16 source CCR 16 CCR destination 8 immediate data V CCR MC68030 USER’S MANUAL Operation SP; (SP) PC SP; SR; STOP (SSP); (SSP); (SSP); PC SSP; PC CCR CCR CCR CCR CCR MOTOROLA ...

Page 91

... User Defined cpRESTORE ea cpSAVE ea cpScc ea cpTRAPcc none # data MOTOROLA Table 3-10. MMU Instructions Operand Size none Invalidate all ATC entries none Invalidate all nonglobal ATC entries none Invalidate ATC entries at effective address none Invalidate nonglobal ATC entries at effective address none ...

Page 92

... Set if arithmetic overflow occurs. This implies that the result cannot be represented in the operand size. Cleared otherwise. C (carry) Set if a carry out of the most significant bit of the operand occurs for an addition. Also set if a borrow occurs in a subtraction. Cleared otherwise. 3- MC68030 USER’S MANUAL MOTOROLA ...

Page 93

... AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI CLR, EXT, NOT, TAS, TST CHK CHK2, CMP2 SUB, SUBI, SUBQ SUBX CAS, CAS2, CMP, CMPI, CMPM DIVS, DUVI MULS, MULU SBCD, NBCD NEG NEGX MOTOROLA =-Decimal Carry Z =- ...

Page 94

... –1 — — — –1 — Result Operand — Most Significant Bit R = Register Tested n = Bit Number r = Shift Count LB = Lower Bound UB = Upper Bound = Boolean AND V = Boolean NOT Rm MC68030 USER’S MANUAL MOTOROLA ...

Page 95

... CC(HS) CS(LO • = Boolean AND + = Boolean Boolean NOT N *Not available for the Bcc instruction. MOTOROLA Table 3-13. Conditional Tests Condition Encoding True 0000 False 0001 High 0010 Low or Same 0011 Carry Clear 0100 Carry Set 0101 Not Equal ...

Page 96

... The operand is binary-coded decimal; operations are per- formed in decimal The register indirect operation Indicates that the operand register points to the memory Location of the instruction operand — the optional mode qualifiers are -, +, (d), and (d,ix) Immediate data that follows the instruction word(s) MC68030 USER’S MANUAL MOTOROLA ...

Page 97

... If condition then — operations else — operations — MOTOROLA The source operand is moved to the destination operand The two operands are exchanged The operands are added The destination operand is subtracted from the source operand The operands are multiplied The source operand is divided by the destination operand ...

Page 98

... Bcc (label BCHG Dn, ea BCHG # data , ea BCLR Dn, ea BCLR # data , ea BFCHG ea {offset:width} BFCLR ea {offset:width} BFEXTS ea {offset:width},Dn BFEXTU ea {offset:width},Dn BFFFO ea {offset:width},Dn BFINS Dn, ea {offset:width} BFSET ea {offset:width} BFTST ea {offset:width} BKPT # data BRA (label BSET Dn, ea BSET # data , ea BSR (label BTST Dn, ea BTST # data , ea MOTOROLA ...

Page 99

... If cpcc true then TRAP DBcc If condition false then (Dn– –1 then DIVS Destination/Source DIVSL DIVU Destination/Source DIVUL EOR Source Destination EORI Immediate Data Destination MOTOROLA cc; Destination Compare Operand cc; cc; Destination 2 Compare 1; Destination 2 Compare Dn; PC Destination Dn; PC) Destination ...

Page 100

... ILLEGAL JMP ea JSR ea LEA ea ,An LINK An, #(displacement 5 LSd Dx,Dy 5 LSd # data ,Dy 5 LSd ea MOVE MOVEA ea ,An MOVE CCR, ea MOVE ea ,CCR MOVE SR, ea MOVE ea ,SR MOVE USP,An MOVE An,USP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM register list, ea MOVEM ea ,register list MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ # data ,Dn MOTOROLA ...

Page 101

... MRn or MRn PTEST If supervisor state then logical address status else TRAP RESET If supervisor state then Assert RSTO Line else TRAP ROL,ROR Destination Rotated by count ROXL, Destination Rotated with X by count ROXR MOTOROLA Operation Rn Destination Destination Destination Destination Destination Destination Destination SR Destintion (SP) (Destination) MMUSR ...

Page 102

... RTD # displacement RTE RTM Rn RTR RTS SBCD Dx,Dy SBCD –(Ax),–(Ay) Scc ea STOP # data SUB ea ,Dn SUB Dn, ea SUBA ea ,An SUBI # data , ea SUBQ # data , ea SUBX Dx,Dy SUBX –(Ax),–(Ay) SWAP Dn TAS ea TRAP # (vector TRAPcc TRAPcc.W # data TRAPcc.L # data TRAPV TST ea UNLK An UNPACK Dx,Dy,#(adjustment MOTOROLA ...

Page 103

... The following code sequence guarantees that SYS_CNTR is correctly incremented. MOVE.W SYS_CNTR,D0 INC_LOOP MOVE.W D0,D1 ADDQ.W #1,D1 CAS.W D0,D1,SYS_CNTR BNE INC_LOOP MOTOROLA get the old value of the counter make a copy of it and increment it if countr value is still the same, update it if not, try again MC68030 USER’S MANUAL Instruction Set Summary 3-25 ...

Page 104

... ESTABLISH FORWARD LINK IN NEW ENTRY MOVE NEW ENTRY POINTER VALUE STILL POINT TO TOP OF STACK, UPDATE THE HEAD POINTER IF NOT, TRY AGAIN ENTRY + NEXT HEAD ENTRY + NEXT Figure 3-2. Linked List Insertion MC68030 USER’S MANUAL ENTRY + NEXT ENTRY + NEXT MOTOROLA ...

Page 105

... SDEMPTY BEFORE DELETING AN ELEMENT: ENTRY HEAD AFTER DELETING AN ELEMENT: ENTRY HEAD MOTOROLA LOAD ADDRESS OF HEAD POINTER INTO A0 MOVE VALUE OF HEAD POINTER INTO D0 CHECK FOR NULL HEAD POINTER IF EMPTY, NOTHING TO DELETE LOAD ADDRESS OF FORWARD LINK INTO A1 PUT FORWARD LINK VALUE STILL POINT TO ENTRY TO BE DELETED, THEN UPDATE HEAD ...

Page 106

... D1 to the LIST-GET pointer and to the address in register A2. If the pointers have not been updated, the CAS2 instruction loads the address in D2 into the LIST_GET pointer and zero into the address in register A2. 3-28 MC68030 USER’S MANUAL MOTOROLA ...

Page 107

... LIST_PUT and LIST_GET to verify that no other routine has inserted another element or deleted the last element. Then the instruction moves zero into both pointers, and the list is empty. MOTOROLA (ALLOCATE NEW LIST ENTRY, LOAD ADDRESS INTO A2) LOAD ADDRESS OF HEAD POINTER INTO A0 ...

Page 108

... IF STILL FIRST ENTRY, SET HEAD AND TAIL POINTERS TO NULL IF NOT, TRY AGAIN SUCCESSFUL ENTRY DELETION, ADDRESS OF DELETED ENTRY IN D1 (MAY BE NULL) ENTRY + LAST + NEXT ENTRY + LAST + NEXT LIST_GET MC68030 USER’S MANUAL ENTRY + LAST + NEXT LIST_GET ENTRY + LAST + NEXT DELETED ENTRY MOTOROLA ...

Page 109

... However, control register locations are not memory locations; therefore not always possible to insert or extract bit fields of a register without affecting other fields within the register. MOTOROLA 31 31 through 2 1 from the most significant bit MC68030 USER’ ...

Page 110

... All previous integer instructions and floating-point external operand accesses complete execution before the NOP begins. The NOP instruction does not synchronize the FPU pipeline; floating-point instructions with floating-point register operand destinations can be executing when the NOP begins. MOTOROLA MC68030 USER’S MANUAL Instruction Set Summary 3-32 ...

Page 111

... Only an external reset can restart a halted processor. (When the processor executes a STOP instruction special type of normal processing state, one without bus cycles stopped, not halted.) MOTOROLA NOTE MC68030 USER’S MANUAL 4-1 ...

Page 112

... MSP when a task switch is performed, providing an efficient means for transferring task-related stack items. The other supervisor stack (ISP) can be used for interrupt control information and workspace area as interrupt handling routines require. 4-2 MC68030 USER’S MANUAL MOTOROLA ...

Page 113

... To prevent a user program from entering the supervisor privilege level, except in a controlled manner, instructions that can alter the S bit in the status register are privileged. The TRAP #n instruction provides controlled access to operating system services for user programs. MOTOROLA MC68030 USER’S MANUAL Processing States ...

Page 114

... S bit of the restored status register. If the frame on top of the stack was generated by a bus fault (bus error or address error exception), the RTE instruction restores the entire saved processor state from the stack. 4-4 MC68030 USER’S MANUAL MOTOROLA ...

Page 115

... Motorola. The memory locations of user program and data accesses are not predefined. Neither are the locations of supervisor data space. During reset, the first two long words beginning at memory location zero in the supervisor program space are used for processor initialization ...

Page 116

... Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Details of exception processing are provided in Section 8 Exception Processing , and Table 8-1 lists the exception vector assignments. 4-6 MC68030 USER’S MANUAL MOTOROLA ...

Page 117

... The general form of the exception stack frame is illustrated in Figure 4-1. Refer to Section 8 Exception Processing for a complete list of exception stack frames. SP Figure 4-1. General Exception Stack Frame MOTOROLA 15 12 STATUS REGISTER PROGRAM COUNTER ...

Page 118

... Figure 5-1. Each signal is explained in a brief paragraph with reference to other sections that contain more detail about the signal and the related operations. FUNCTION CODES ADDRESS BUS DATA BUS TRANSFER SIZE ASYNCHRONOUS BUS CONTROL CACHE CONTROL Figure 5-1. Functional Signal Groups MOTOROLA IPL0 FC2-FC0 IPL1 IPL2 A31-A0 IPEND AVEC D31-D0 BR SIZ0 BG ...

Page 119

... AS Indicates that a valid address is on the bus. DS Indicates that valid data placed on the data bus by an external device or has been placed on the data bus by the MC68030. Provides an enable signal for external data buffers. MC68030 USER’S MANUAL Function MOTOROLA ...

Page 120

... Clock CLK Power Supply Ground GND MOTOROLA Bus response signals that indicate the requested data transfer operation is completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Bus response signal that indicates a port size of 32 bits and that data may be latched on the next falling clock edge ...

Page 121

... With A0, A1, DSACK0, DSACK1, and STERM, SIZ0 and SIZ1 define the number of bits transferred on the data bus. Refer to 7.2.1 Dynamic Bus Sizing for more information on the size signals and their use in dynamic bus sizing. 5-4 MC68030 USER’S MANUAL MOTOROLA ...

Page 122

... This three-state output indicates that a valid address is on the address bus. The function code, size, and read/write signals are also valid when AS is asserted. Refer to 7.1.3 Address Strobe for information about the relationship bus operation. MOTOROLA MC68030 USER’S MANUAL Signal Description ...

Page 123

... This input is a bus handshake signal indicating that the addressed port size is 32 bits and that data latched on the next falling clock edge for a read cycle. This signal applies only to synchronous operation. Refer to 7.1.7 Bus Cycle Termination Signals for more information about the relationship of STERM to bus operation. 5-6 MC68030 USER’S MANUAL MOTOROLA ...

Page 124

... This input signal indicates that the accessed device can operate in the burst mode and can supply at least one more long word for the instruction or data cache. Refer to 7.3.7 Burst Operation Cycles for information about burst mode operation. MOTOROLA MC68030 USER’S MANUAL Signal Description ...

Page 125

... Bus Request (BR) This input signal indicates that an external device needs to become the bus master. This is typically a "wire-ORed” input (but does not need to be constructed from open-collector devices). Refer to 7.7 Bus Arbitration for more information. 5-8 MC68030 USER’S MANUAL MOTOROLA ...

Page 126

... The bus error signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to 7.5 Bus Exception Control Cycles for a description of the effects of BERR on bus operations. MOTOROLA MC68030 USER’S MANUAL Signal Description ...

Page 127

... The microsequencer status signal indicates the state of the internal microsequencer. The varying number of clocks for which this signal is asserted indicates instruction boundaries, pending exceptions, and the halted condition. Refer to Section 12 Applications Information for a description of the use of this signal by an emulator. 5-10 MC68030 USER’S MANUAL MOTOROLA ...

Page 128

... Information and Mechanical Data describes the groupings of V connections, and Section 12 Applications Information describes a typical power supply interface. 5.14 SIGNAL SUMMARY Table 5-2 provides a summary of the electrical characteristics of the signals discussed in this section. 5-11 power supply, positive with respect to ground. CC MC68030 USER’S MANUAL and ground CC MOTOROLA ...

Page 129

... Yes Low — Low — Low — Low Yes Low Yes Low — Low — Low No Low — Low — Low No Low — Low No Low — Low — Low — Low — Low No Low No — — — — — — MOTOROLA ...

Page 130

... Regardless of whether or not the required operand is located in one of the on-chip caches, the address translation cache of the MMU performs logical-to-physical address translation in parallel with the cache lookup in case an external cycle is required. MOTOROLA MC68030 USER’S MANUAL 6-1 ...

Page 131

... On-Chip Cache Memories Figure 6-1. Internal Caches and the MC68030 6-2 MC68030 USER’S MANUAL MOTOROLA ...

Page 132

... Therefore, the state of the corresponding CI bits in the MMU are also ignored. The MMU is used to validate all accesses that require external bus cycles; an address translation must be available and valid, protections are checked, and the CIOUT signal is asserted appropriately. MOTOROLA MC68030 USER’S MANUAL On-Chip Cache Memories 6-3 ...

Page 133

... Dynamic RAMs supporting fast access modes (page, nibble, or static column) are easily employed to support the MC68030 burst mode. 6-4 MC68030 USER’S MANUAL MOTOROLA ...

Page 134

... A3–A2) is set cache hit, the word selected by address bit A1 is supplied to the instruction pipe. When the address and function code bits do not match or the requested entry is not valid, a miss occurs. The bus controller initiates a long-word prefetch operation for the required MOTOROLA LONG-WORD SELECT INDEX ...

Page 135

... The value in the data cache might be used by another instruction before the external write cycle has completed, although this should not have any adverse consequences. Refer to 7.6 Bus Synchronization for the details of bus synchronization. 6-6 MC68030 USER’S MANUAL MOTOROLA ...

Page 136

... Thus, an aligned long-word data write may replace a previously valid entry; whereas, a misaligned data write or a write of data that is not long word may invalidate a previously valid entry or entries. MOTOROLA LONG-WORD SELECT INDEX ...

Page 137

... RESULT IN A CACHE MISS, b8-b9 RESULT IN A CACHE HIT) Figure 6-4. No-Write-Allocation and Write-Allocation Mode Examples 6-8 b0-b3 b4-b7 WRITE ALLOCATE A) START EXTERNAL CYCLE B) b2-b3 b2'-b3' A) START EXTERNAL CYCLE B) b8-b9 b8'-b9' MC68030 USER’S MANUAL b8-bB bC-bF WRITE ALLOCATE A) START EXTERNAL CYCLE B) b2-b3 b2'-b3' A) START EXTERNAL CYCLE B) b8-b9 b8'-b9' MOTOROLA ...

Page 138

... Similarly, the processor assumes that a 16-bit termination signal indicates that all 16 bits are valid. If the device cannot supply its full port width of data, it must assert CIIN for all bus cycles corresponding to a cache entry. MOTOROLA MC68030 USER’S MANUAL On-Chip Cache Memories ...

Page 139

... If the port size is 32 bits, the processor performs two accesses, one for each cache entry. 6-10 (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) MC68030 USER’S MANUAL MOTOROLA ...

Page 140

... If the bus error occurs on a read cycle for a portion of the required operand (not the remaining bytes of the cache entry loaded into the data cache, the processor immediately takes a bus error exception. If MOTOROLA (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) (UNABLE TO LOCATE ART) MC68030 USER’ ...

Page 141

... However, data from the burst fill cycles is not available to the EU until the burst operation is complete. Since the microsequencer makes two separate requests for misaligned data operands, only the first portion of the misaligned operand returned during a 6-12 MC68030 USER’S MANUAL MOTOROLA ...

Page 142

... The second access, at address $10 corresponding to the second cache line, requests a burst fill and the processor asserts CBREQ. During this burst operation, long words $10, $14, $18, and $1C are all filled in that order. Figure 6-13. Deferred Burst Filling Example MOTOROLA BURST OPERATION CYCLE 2 CYCLE 3 ...

Page 143

... CBREQ. Once the burst terminates, the microsequencer requests a read cycle for the second portion. Since the burst terminated abnormally for the second cycle of the burst, the data cache 6-14 MC68030 USER’S MANUAL MOTOROLA ...

Page 144

... MOVEC instruction. For example, loading a long word in which bits 3 and 11 are set into the CACR clears both caches. Bits 31-14 and 7-5 are reserved for Motorola definition. They are currently read as zeros and are ignored when written. For future compatibility, writes should not set these bits ...

Page 145

... MOVEC instruction loads a one into the CED bit of the CACR, regardless of the states of the ED and FD bits. The CED bit is always read as a zero. 6-16 MC68030 USER’S MANUAL MOTOROLA ...

Page 146

... The processor clears only the specified long word by clearing the valid bit for the entry at the time a MOVEC instruction loads a one into the CEI bit of the CACR, regardless of the states of the EI and FI bits. The CEI bit is always read as a zero. MOTOROLA MC68030 USER’S MANUAL On-Chip Cache Memories ...

Page 147

... The bits of this field correspond to bits 7-2 of addresses; they specify the index and a long word of a cache line. Although only the index field is used currently, all 32 bits of the register are implemented and are reserved for use by Motorola. 31 CACHE FUNCTION ADDRESS Figure 6-15 ...

Page 148

... The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. MOTOROLA MC68030 USER’S MANUAL 7-1 ...

Page 149

... In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. 7-2 SYNC DELAY MC68030 USER’S MANUAL MOTOROLA ...

Page 150

... The function code signals (FC0–FC2) are also driven at the beginning of a bus cycle. These three signals select one of eight address spaces (refer to Table 4-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved MOTOROLA ...

Page 151

... Bus Operation for user definition and two are reserved by Motorola for future use. The function code signals are valid while AS is asserted. At the beginning of a bus cycle, the size signals (SIZ0 and SIZ1) are driven along with ECS and the FC0–FC2. SIZ0 and SIZ1 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) or during a cache fill operation from a device with a port size that is less than 32 bits ...

Page 152

... These signals also indicate to the processor the size of the port for the bus cycle just completed, as shown in Table 7-1. Refer to 7.3.1 Asynchronous Read Cycle for timing relationships of DSACK0 and DSACK1. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-5 ...

Page 153

... DSACKx inputs. Refer to Table 7-1 for DSACKx encodings and assertion results. 7-6 MC68030 USER’S MANUAL MOTOROLA ...

Page 154

... OP0, and OP3 is the least significant byte. The two bytes of a word- length operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow. MOTOROLA Result Insert Wait States in Current Bus Cycle Complete Cycle — ...

Page 155

... A0 and A1 indicate the byte offset from the base. Table 7-3 shows the encodings of A0 and A1 and the corresponding byte offsets from the long-word base. 7-8 OP0 OP1 OP2 15 WORD OPERAND OP2 BYTE OPERAND MC68030 USER’S MANUAL 0 OP3 0 OP3 7 0 OP3 MOTOROLA ...

Page 156

... PRn and Nn are not required and can be replaced by “don't cares”. Table 7-2. Size Signal Encoding SIZ1 SIZ0 MOTOROLA OP1 OP2 1 2 ROUTING AND DUPLICATION D23-D16 D15-D8 BYTE 1 BYTE 2 BYTE 1 16-BIT PORT BYTE 3 b 8-BIT PORT Table 7-3 ...

Page 157

... The bus cycle transfers the remaining bytes to the word-size port. Figure 7- 6 shows the timing of the bus transfer signals for this operation. 7-10 MC68030 USER’S MANUAL MOTOROLA ...

Page 158

... Table 7-5. MC68030 Internal to External Data Bus. (Table did not make it over in the conversion from Word) 31 OP0 D31 DATA BUS WORD MEMORY MSB OP0 OP2 Figure 7-5. Example of Long-Word Transfer to Word Port MOTOROLA LONG WORD OPERAND OP1 OP2 D16 MC68EC030 SIZ1 SIZ0 A1 LSB 0 ...

Page 159

... Figure 7-8 shows the associated bus transfer signal timing. 7- OP0 OP1 WORD WRITE WORD WRITE LONG WORD OPERAND WRITE TO 16-BIT PORT MC68030 USER’S MANUAL S4 OP2 OP3 MOTOROLA ...

Page 160

... For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. MOTOROLA 0 OP3 D24 MC68EC030 ...

Page 161

... SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 Figure 7-8. Word Operand Write Timing (8-Bit Data Port) 7- OP2 OP3 OP3 OP3 OP2 OP3 OP3 OP3 BYTE WRITE BYTE WRITE WORD OPERAND WRITE MC68030 USER’S MANUAL S4 MOTOROLA ...

Page 162

... Figure 7-14 shows the equivalent operation for a cachable data read cycle. 31 OP0 DATA BUS D31 WORD MEMORY MSB XXX OP1 OP3 Figure 7-9. Misaligned Long-Word Transfer to Word Port Example MOTOROLA LONG WORD OPERAND OP1 OP2 D16 MC68EC030 A0 SIZ1 SIZ0 A1 LSB 0 ...

Page 163

... DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BYTE WRITE Figure 7-10. Misaligned Long-Word Transfer to Word Port 7- OP0 OP1 OP0 OP2 OP1 OP1 OP2 OP2 WORD WRITE LONG WORD OPERAND WRITE MC68030 USER’S MANUAL OP3 OP3 OP3 OP3 BYTE WRITE MOTOROLA ...

Page 164

... MSB PR OP1 OP3 N1 Figure 7-11. Misaligned Cachable Long-Word Transfer from Word Port Example 15 WORD OPERAND OP2 D31 DATA BUS WORD MEMORY MSB XXX OP3 Figure 7-12. Misaligned Word Transfer to Word Port Example MOTOROLA 0 OP2 OP3 31 CACHE ENTRIES PR OP0 31 OP3 N D16 MC68EC030 SIZ1 SIZ0 A1 ...

Page 165

... A1 A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE Figure 7-13. Misaligned Word Transfer to Word Port 7- OP2 OP2 OP3 OP2 BYTE WRITE WORD OPERAND WRITE TO A1/A0=01 MC68030 USER’S MANUAL S4 OP3 OP3 OP3 OP3 MOTOROLA ...

Page 166

... This table shows that bus cycle throughput is significantly affected by port size and alignment. The MC68030 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications. MOTOROLA Number of Bus Cycles 00 01 ...

Page 167

... DSACK1 OP2 OP3 D0 LMB LSB XXX OP0 OP3 XXX MC68030 USER’S MANUAL CACHE ENTRY OP3 N DSACK0 MC68EC030 MEMORY CONTROL SIZ1 SIZ0 DSACK1 DSACK0 MOTOROLA ...

Page 168

... A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 Figure 7-16. Misaligned Write Cycles to Long-Word Port MOTOROLA OP0 OP0 OP1 OP0 BYTE WRITE LONG WORD OPERAND WRITE MC68030 USER’S MANUAL Bus Operation S2 S4 OP1 OP2 OP3 ...

Page 169

... OP2 OP3 31 CACHE ENTRIES PR2 PR1 31 OP1 OP2 D0 MC68EC030 LMB LSB SIZ1 SIZ0 PR OP0 0 0 OP3 MC68030 USER’S MANUAL 0 PR OP0 0 OP3 N MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...

Page 170

... The other bytes are not selected, which prevents incorrect accesses in sensitive areas such as I/O. Figure 7-18 shows a logic diagram for one method for generating byte data enable signals for 16- and 32-bit ports from the size and address encodings and the read/write signal. MOTOROLA Data Bus Active Sections A1 A0 ...

Page 171

... STERM with each one, until the cache line is full. For further information about filling the cache, both entry fills and burst mode fills, refer to 6.1.3 Cache Filling, 7.3.4 Synchronous Read Cycle, 7.3.5 Synchronous Write Cycle, and 7.3.7 Burst Operation Cycles, which discuss in detail the required bus cycles. 7-24 MC68030 USER’S MANUAL MOTOROLA ...

Page 172

... Therefore, in the case of a misaligned data transfer where the first portion of the operand results in a cache hit (but the bus controller did not begin an external cycle and then abort it) and the second portion in a cache miss, OCS is asserted for the second portion of the operand. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-25 ...

Page 173

... UUD = UPPER UPPER DATA (32-BIT PORT) UMD = UPPER MIDDLE DATA (32-BIT PORT) LMD = LOWER MIDDLE DATA (32-BIT PORT) LLD = LOWER LOWER DATA (32-BIT PORT UPPER DATA (16-BIT PORT LOWER DATA (16-BIT PORT) MC68030 USER’S MANUAL UUD UMD LMD LLD UD LD MOTOROLA ...

Page 174

... The BERR and/or HALT signals can be asserted after the DSACKx signal(s) is asserted. BERR and/or HALT must be asserted within the time given as parameter #48, after DSACKx is asserted in any asynchronous system. If this maximum delay time is violated, the processor may exhibit erratic behavior. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-27 ...

Page 175

... BERR/HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time specified by parameter #47B), no wait states are inserted. The bus cycle runs at its maximum speed (three clocks per cycle) for bus cycles terminated with DSACKx. 7-28 MC68030 USER’S MANUAL MOTOROLA ...

Page 176

... Again, the exact timing for these subsequent cycles is controlled by the timing of STERM for each of these cycles, and wait cycles can be inserted as necessary. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-29 ...

Page 177

... In addition, the bus master is responsible for de-skewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. An additional paragraph describes burst mode transfers. 7-30 NOTE MC68030 USER’S MANUAL MOTOROLA ...

Page 178

... DBEN inactive to disable the data buffers. SIZ0–SIZ1 become valid, indicating the number of bytes requested to be transferred. CIOUT also becomes valid, indicating the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-31 ...

Page 179

... REMOVE DATA FROM D31-D0 2) NEGATE DSACK EXTERNAL DEVICE 1) DECODE ADDRESS 2) PLACE DATA ON D31-D324 OR (BASED ON A1,A0, CACHE AND BUS WIDTH) 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) REMOVE DATA FROM D31-D0 2) NEGATE DSACK MC68030 USER’S MANUAL PRESENT DATA PRESENT DATA D23-D16 OR D15-D8 OR D7-D0 MOTOROLA ...

Page 180

... WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD READ Figure 7-21. Asynchronous Byte and Word Read Cycles — 32-Bit Port MOTOROLA BYTE OP2 OP3 OP3 BYTE READ MC68030 USER’S MANUAL Bus Operation OP3 BYTE READ ...

Page 181

... AS DS CIOUT DSACK1 DSACK0 DBEN D31-D24 OP0 D23-D16 D15-D8 D7-D0 BYTE READ Figure 7-22. Long-Word Read — 8-Bit Port with CIOUT Asserted MOTOROLA 3-BYTE WORD OP1 BYTE READ BYTE READ LONG WORD OPERAND READ FROM 8-BIT PORT MC68030 USER’S MANUAL ...

Page 182

... LONG WORD OPERAND READ FROM 16-BIT PORT Figure 7-23. Long-Word Read — 16-Bit and 32-Bit Port 7- WORD OP2 OP0 OP1 OP3 WORD READ MC68030 USER’S MANUAL LONG WORD OP0 OP1 OP2 OP3 LONG WORD READ FROM 32- BIT PORT MOTOROLA ...

Page 183

... (whichever it detects first). The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-37 ...

Page 184

... NEGATE AS AND DS 2) REMOVE DATA FROM D31-D0 3) NEGATE DBEN START NEXT CYCLE Figure 7-24. Asynchronous Write Cycle Flowchart 7-38 EXTERNAL DEVICE 1) DECODE ADDRSS 2) STORE DATA FROM D31-D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) NEGATE DSACKx MC68030 USER’S MANUAL ACCEPT DATA MOTOROLA ...

Page 185

... During S0, the processor places a valid address on A0–A31 and valid function codes on FC0–FC2. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SIZ0–SIZ1 become valid, indicating the number of bytes to be transferred. CIOUT also becomes valid, indicating MOTOROLA ...

Page 186

... Bus Operation the state of the MMU CI bit in the address translation descriptor or in the appropriate TTx register. 7-40 MC68030 USER’S MANUAL MOTOROLA ...

Page 187

... WORD SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE Figure 7-26. Asynchronous Byte and Word Write Cycles — 32-Bit Port MOTOROLA BYTE OP3 OP2 OP3 OP3 OP2 OP3 OP3 OP3 BYTE WRITE MC68030 USER’S MANUAL ...

Page 188

... Figure 7-27. Long-Word Operand Write — 8-Bit Port 7- 3-BYTE WORD OP1 OP1 OP2 OP3 BYTE WRITE BYTE WRITE LONG WORD OPERAND READ TO 8-BIT PORT MC68030 USER’S MANUAL BYTE OP2 OP3 OP3 OP3 OP2 OP3 OP3 OP3 BYTE WRITE MOTOROLA ...

Page 189

... R/W ECS OCS AS DS DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 WORD WRITE LONG WORD OPERAND WRITE TO 16-BIT PORT Figure 7-28. Long-Word Operand Write — 16-Bit Port MOTOROLA WORD OP0 OP2 OP1 OP3 OP2 OP2 OP3 OP3 WORD WRITE MC68030 USER’S MANUAL ...

Page 190

... The external device must keep DSACKx asserted until it detects the negation (whichever it detects first). The device must negate DSACKx within approximately one clock period after sensing the negation DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 7-44 MC68030 USER’S MANUAL MOTOROLA ...

Page 191

... TTx register. State 1 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor asserts DS during S1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-45 ...

Page 192

... TERMINATE CYCLE 1) NEGATE DSACKx MC68030 USER’S MANUAL A IF CAS2 INSTRUCTION AND ONLY ONE OPERAND READ, THEN OPERANDS DO NOT MATCH, THEN ELSE CAS2 INSTRUCTION AND ONLY ONE OPERAND WRITTEN, THEN ELSE MOTOROLA ...

Page 193

... S6-S11 are omitted if no write cycle is required write cycle is required, the R/W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S8. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-47 ...

Page 194

... CIIN CIOUT DSACK1 DSACK0 DBEN D31-D24 D23-D16 D15-D8 D7-D0 BERR HALT BG Figure 7-30. Asynchronous Byte Read-Modify-Write Cycle — 32-Bit Port (TAS Instruction with CIOUT or CIIN Asserted) 7- OP3 INDIVISIBLE CYCLE MC68030 USER’S MANUAL S10 S0 OP3 OP3 OP3 OP3 NEXT CYCLE MOTOROLA ...

Page 195

... D16–D23, D8–D15, and D0–D7). SIZ0–SIZ1 and A0–A1 select the data bus sections has not already done so, the device asserts DSACKx when it has successfully stored the data. State 10 The processor issues no new control signals during S10. MOTOROLA MC68030 USER’S MANUAL Bus Operation 7-49 ...

Page 196

... STERM can be used to provide more decision time in an external cache design than is available with DSACKx for three-clock accesses. Figure 7- flowchart of a synchronous long-word read cycle. Byte and word operations are similar. Figure 7- functional timing diagram of a synchronous long-word read cycle. 7-50 MC68030 USER’S MANUAL MOTOROLA ...

Page 197

... The processor also asserts DS during S1. If the burst mode is enabled for the appropriate on-chip cache and all four long words of the cache entry are invalid, (i.e., four long words can be read in), CBREQ is asserted. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MOTOROLA EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS ...

Page 198

... STERM. If STERM is recognized, the processor latches the incoming data at the end of S2. If the selected data is not to be cached for the 7- CLK A31-A0 FC2-FC0 SIZ1 SIZ0 R/W ECS OCS AS DS DSACK1 DSACK0 STERM CIIN CIOUT CBREQ CBACK D31-D0 DBEN MC68030 USER’S MANUAL MOTOROLA ...

Page 199

... AS and the required assertion of STERM for any two-clock synchronous bus cycle. The system must qualify a memory write with the assertion ensure that the write is not aborted by internal conditions within the MC68030. MOTOROLA MC68030 USER’S MANUAL Bus Operation ...

Page 200

... The processor also asserts DBEN during S1, which may be used to enable the external data buffers. In addition, the ECS (and OCS, if asserted) signal is negated during S1. 7-54 ACCEPT DATA 1) DECODE ADDRESS 2) STORE DATA ON D31-D0 3) ASSERT SYNCHRONOUS TERMINATION (STERM) TERMINATE CYCLE 1) NEGATE STERM MC68030 USER’S MANUAL EXTERNAL DEVICE MOTOROLA ...

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