ST10F272B_12 STMICROELECTRONICS [STMicroelectronics], ST10F272B_12 Datasheet - Page 113

• Manufacturer Part Number: ST10F272B_12
• Description: 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272B/ST10F272E
21.3.2
21.3.3
Exiting stand-by mode
After the system has entered the Stand-by Mode, the procedure to exit this mode consists of
a standard power-on sequence, with the only difference that the RAM is already powered
through V
It is recommended to held the device under RESET (RSTIN pin forced low) until external
VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V18 becomes higher than about 1.0V, there
is no warranty that the device stays under reset status if RSTIN is at high level during power
ramp up. So, it is important the external hardware is able to guarantee a stable ground level
on RSTIN along the power-on phase, without any temporary glitch.
The external hardware shall be responsible to drive low the RSTIN pin until the VDD is
stable, even though the internal LVD is active.
Once the internal reset signal goes low, the RAM (still frozen) power supply is switched to
the main V
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.
Real time clock and stand-by mode
When stand-by mode is entered (turning off the main supply V
counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide
the reference to the counter. This is not possible if the main oscillator is used as reference
for the counter: Being the main oscillator powered by V
oscillator is stopped.
Warning:
18SB
18
.
internal reference (derived from V
During power-off phase, it is important that the external
hardware maintains a stable ground level on RSTIN pin,
without any glitch, in order to avoid spurious exiting from
reset status with unstable power supply.
Doc ID 11917 Rev 3
STBY
pin external voltage).
DD
, once this is switched off, the
DD
), the Real Time Clock
Power reduction modes
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